67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
42 lines
2.7 KiB
LLVM
42 lines
2.7 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: OpName %[[#Foo:]] "foo"
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; CHECK-DAG: OpName %[[#Ptr1:]] "_arg1"
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; CHECK-DAG: OpName %[[#Ptr2:]] "_arg2"
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; CHECK-DAG: OpName %[[#Ptr3:]] "_arg3"
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; CHECK-DAG: OpName %[[#Ptr4:]] "_arg4"
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; CHECK-DAG: OpName %[[#Ptr5:]] "_arg5"
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; CHECK-DAG: OpDecorate %[[#Ptr1]] NonReadable
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; CHECK-DAG: OpDecorate %[[#Ptr2]] Alignment 128
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; CHECK-DAG: OpDecorate %[[#Ptr2]] NonReadable
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; CHECK-DAG: OpDecorate %[[#Ptr3]] Alignment 128
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; CHECK-DAG: OpDecorate %[[#Ptr3]] NonReadable
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; CHECK-DAG: OpDecorate %[[#Ptr4]] Alignment 128
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; CHECK-DAG: OpDecorate %[[#Ptr4]] NonReadable
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; CHECK-DAG: OpDecorate %[[#Ptr5]] UserSemantic "Unknown format"
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; CHECK: %[[#Foo]] = OpFunction
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; CHECK-NEXT: %[[#Ptr1]] = OpFunctionParameter
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; CHECK-NEXT: %[[#Ptr2]] = OpFunctionParameter
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; CHECK-NEXT: %[[#Ptr3]] = OpFunctionParameter
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; CHECK-NEXT: %[[#Ptr4]] = OpFunctionParameter
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; CHECK-NEXT: %[[#Ptr5]] = OpFunctionParameter
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; CHECK: OpFunctionEnd
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@.str.0 = private unnamed_addr addrspace(1) constant [16 x i8] c"../prefetch.hpp\00", section "llvm.metadata"
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@.str.1 = private unnamed_addr addrspace(1) constant [5 x i8] c"{25}\00", section "llvm.metadata"
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@.str.2 = private unnamed_addr addrspace(1) constant [13 x i8] c"{44:128}{25}\00", section "llvm.metadata"
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@.str.3 = private unnamed_addr addrspace(1) constant [15 x i8] c"{44:\22128\22}{25}\00", section "llvm.metadata"
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@.str.4 = private unnamed_addr addrspace(1) constant [13 x i8] c"{44,128}{25}\00", section "llvm.metadata"
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@.str.5 = private unnamed_addr addrspace(1) constant [15 x i8] c"Unknown format\00", section "llvm.metadata"
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define spir_kernel void @foo(ptr addrspace(1) %_arg1, ptr addrspace(1) %_arg2, ptr addrspace(1) %_arg3, ptr addrspace(1) %_arg4, ptr addrspace(1) %_arg5) {
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entry:
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%r1 = tail call ptr addrspace(1) @llvm.ptr.annotation.p1.p1(ptr addrspace(1) %_arg1, ptr addrspace(1) @.str.1, ptr addrspace(1) @.str.0, i32 80, ptr addrspace(1) null)
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%r2 = tail call ptr addrspace(1) @llvm.ptr.annotation.p1.p1(ptr addrspace(1) %_arg2, ptr addrspace(1) @.str.2, ptr addrspace(1) @.str.0, i32 80, ptr addrspace(1) null)
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%r3 = tail call ptr addrspace(1) @llvm.ptr.annotation.p1.p1(ptr addrspace(1) %_arg3, ptr addrspace(1) @.str.3, ptr addrspace(1) @.str.0, i32 80, ptr addrspace(1) null)
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%r4 = tail call ptr addrspace(1) @llvm.ptr.annotation.p1.p1(ptr addrspace(1) %_arg4, ptr addrspace(1) @.str.4, ptr addrspace(1) @.str.0, i32 80, ptr addrspace(1) null)
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%r5 = tail call ptr addrspace(1) @llvm.ptr.annotation.p1.p1(ptr addrspace(1) %_arg5, ptr addrspace(1) @.str.5, ptr addrspace(1) @.str.0, i32 80, ptr addrspace(1) null)
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ret void
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}
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