7b766a6f50
This patch support ND CMOV instructions and CFCMOV instructions. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
96 lines
2.5 KiB
LLVM
96 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+cf -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+cf -x86-cmov-converter=false -verify-machineinstrs | FileCheck %s
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define i8 @cfcmov8rr(i8 %0) {
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; CHECK-LABEL: cfcmov8rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpb $1, %dil
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; CHECK-NEXT: cfcmovel %edi, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%2 = icmp eq i8 %0, 1
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%3 = select i1 %2, i8 %0, i8 0
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ret i8 %3
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}
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define i16 @cfcmov16rr(i16 %0) {
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; CHECK-LABEL: cfcmov16rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpw $1, %di
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; CHECK-NEXT: cfcmovnel %edi, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%2 = icmp ne i16 %0, 1
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%3 = select i1 %2, i16 %0, i16 0
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ret i16 %3
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}
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define i32 @cfcmov32rr(i32 %0) {
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; CHECK-LABEL: cfcmov32rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpl $2, %edi
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; CHECK-NEXT: cfcmovael %edi, %eax
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; CHECK-NEXT: retq
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%2 = icmp ugt i32 %0, 1
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%3 = select i1 %2, i32 %0, i32 0
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ret i32 %3
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}
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define i64 @cfcmov64rr(i64 %0) {
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; CHECK-LABEL: cfcmov64rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: cfcmoveq %rdi, %rax
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; CHECK-NEXT: retq
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%2 = icmp ult i64 %0, 1
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%3 = select i1 %2, i64 %0, i64 0
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ret i64 %3
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}
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define i8 @cfcmov8rr_inv(i8 %0) {
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; CHECK-LABEL: cfcmov8rr_inv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpb $1, %dil
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; CHECK-NEXT: cfcmovnel %edi, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%2 = icmp eq i8 %0, 1
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%3 = select i1 %2, i8 0, i8 %0
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ret i8 %3
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}
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define i16 @cfcmov16rr_inv(i16 %0) {
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; CHECK-LABEL: cfcmov16rr_inv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpw $1, %di
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; CHECK-NEXT: cfcmovel %edi, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%2 = icmp ne i16 %0, 1
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%3 = select i1 %2, i16 0, i16 %0
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ret i16 %3
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}
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define i32 @cfcmov32rr_inv(i32 %0) {
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; CHECK-LABEL: cfcmov32rr_inv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpl $2, %edi
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; CHECK-NEXT: cfcmovbl %edi, %eax
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; CHECK-NEXT: retq
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%2 = icmp ugt i32 %0, 1
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%3 = select i1 %2, i32 0, i32 %0
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ret i32 %3
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}
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define i64 @cfcmov64rr_inv(i64 %0) {
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; CHECK-LABEL: cfcmov64rr_inv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpq $2, %rdi
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; CHECK-NEXT: cfcmovaeq %rdi, %rax
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; CHECK-NEXT: retq
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%2 = icmp ule i64 %0, 1
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%3 = select i1 %2, i64 0, i64 %0
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ret i64 %3
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}
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