Anton Sidorenko 09fc178180

[RISCV] Add scheduling model for Syntacore SCR7 (#108814) ...

Syntacore SCR7 is rv64imafdcv_zba_zbb_zbc_zbs_zkn.
Scheduling model for RVV will be added later.
Overview: https://syntacore.com/products/scr7

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Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev@syntacore.com>
Co-authored-by: Elena Lepilkina <elena.lepilkina@syntacore.com>

2024-09-17 18:52:55 +03:00

..

SiFive7

[RISCV] Model integer min max instructions from Zbb execute in late-B ALU

2024-03-14 06:02:53 -07:00

SiFiveP400

[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)

2024-08-19 09:41:42 -04:00

SiFiveP600

[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)

2024-05-30 08:47:27 -07:00

SyntacoreSCR

[RISCV] Add scheduling model for Syntacore SCR7 (#108814)

2024-09-17 18:52:55 +03:00

XiangShan

[RISCV] Add sched model for XiangShan-NanHu (#70232)

2024-02-12 15:00:54 +08:00

different-lmul-instruments.s

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different-sew-instruments.s

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disable-im.s

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fractional-lmul-data.s

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lit.local.cfg

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lmul-instrument-at-start.s

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lmul-instrument-in-middle.s

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lmul-instrument-in-region.s

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lmul-instrument-straddles-region.s

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multiple-same-lmul-instruments.s

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multiple-same-sew-instruments.s

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needs-sew-but-only-lmul.s

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no-vsetvli-to-start.s

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riscv-lmul-instrument-no-data-is-err.s

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riscv-sew-instrument-no-data-is-err.s

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sew-instrument-at-start.s

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sew-instrument-in-middle.s

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sew-instrument-in-region.s

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sew-instrument-straddles-region.s

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unknown-instrument-is-err.s

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unknown-lmul-is-err.s

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unknown-sew-is-err.s

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vle-vse.s

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vsetivli-lmul-instrument.s

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vsetivli-lmul-sew-instrument.s

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vsetvli-lmul-instrument.s

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vsetvli-lmul-sew-instrument.s

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