1595f36d6d
and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. llvm-svn: 179118
446 lines
15 KiB
C++
446 lines
15 KiB
C++
//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEISelLowering.h"
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#include "MipsRegisterInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
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cl::desc("MIPS: Enable tail calls."), cl::init(false));
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MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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: MipsTargetLowering(TM) {
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// Set up the register classes
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clearRegisterClasses();
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addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
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if (HasMips64)
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addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
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if (Subtarget->hasDSP()) {
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MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
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for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
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addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
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// Expand all builtin opcodes.
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for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
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setOperationAction(Opc, VecTys[i], Expand);
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setOperationAction(ISD::LOAD, VecTys[i], Legal);
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setOperationAction(ISD::STORE, VecTys[i], Legal);
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setOperationAction(ISD::BITCAST, VecTys[i], Legal);
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}
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}
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if (!TM.Options.UseSoftFloat) {
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addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
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// When dealing with single precision only, use libcalls
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if (!Subtarget->isSingleFloat()) {
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if (HasMips64)
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addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
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else
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addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
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}
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}
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::MULHS, MVT::i32, Custom);
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setOperationAction(ISD::MULHU, MVT::i32, Custom);
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if (HasMips64)
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setOperationAction(ISD::MUL, MVT::i64, Custom);
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setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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setTargetDAGCombine(ISD::ADDE);
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setTargetDAGCombine(ISD::SUBE);
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computeRegisterProperties();
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}
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const MipsTargetLowering *
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llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
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return new MipsSETargetLowering(TM);
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}
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bool
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MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
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MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
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switch (SVT) {
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case MVT::i64:
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case MVT::i32:
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if (Fast)
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*Fast = true;
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return true;
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default:
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return false;
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}
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}
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SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch(Op.getOpcode()) {
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case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
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case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
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case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
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case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
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case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
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case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
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case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
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}
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return MipsTargetLowering::LowerOperation(Op, DAG);
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}
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// selectMADD -
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// Transforms a subgraph in CurDAG if the following pattern is found:
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// (addc multLo, Lo0), (adde multHi, Hi0),
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// where,
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// multHi/Lo: product of multiplication
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// Lo0: initial value of Lo register
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// Hi0: initial value of Hi register
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// Return true if pattern matching was successful.
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static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
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// ADDENode's second operand must be a flag output of an ADDC node in order
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// for the matching to be successful.
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SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
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if (ADDCNode->getOpcode() != ISD::ADDC)
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return false;
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SDValue MultHi = ADDENode->getOperand(0);
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SDValue MultLo = ADDCNode->getOperand(0);
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SDNode *MultNode = MultHi.getNode();
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unsigned MultOpc = MultHi.getOpcode();
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// MultHi and MultLo must be generated by the same node,
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if (MultLo.getNode() != MultNode)
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return false;
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// and it must be a multiplication.
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if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
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return false;
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// MultLo amd MultHi must be the first and second output of MultNode
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// respectively.
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if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
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return false;
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// Transform this to a MADD only if ADDENode and ADDCNode are the only users
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// of the values of MultNode, in which case MultNode will be removed in later
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// phases.
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// If there exist users other than ADDENode or ADDCNode, this function returns
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// here, which will result in MultNode being mapped to a single MULT
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// instruction node rather than a pair of MULT and MADD instructions being
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// produced.
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if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
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return false;
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DebugLoc DL = ADDENode->getDebugLoc();
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// Initialize accumulator.
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SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
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ADDCNode->getOperand(1),
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ADDENode->getOperand(1));
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// create MipsMAdd(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
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SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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ACCIn);
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// replace uses of adde and addc here
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if (!SDValue(ADDCNode, 0).use_empty()) {
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SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
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SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
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LoIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
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}
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if (!SDValue(ADDENode, 0).use_empty()) {
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SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
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SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
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HiIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
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}
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return true;
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}
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// selectMSUB -
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// Transforms a subgraph in CurDAG if the following pattern is found:
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// (addc Lo0, multLo), (sube Hi0, multHi),
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// where,
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// multHi/Lo: product of multiplication
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// Lo0: initial value of Lo register
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// Hi0: initial value of Hi register
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// Return true if pattern matching was successful.
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static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
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// SUBENode's second operand must be a flag output of an SUBC node in order
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// for the matching to be successful.
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SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
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if (SUBCNode->getOpcode() != ISD::SUBC)
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return false;
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SDValue MultHi = SUBENode->getOperand(1);
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SDValue MultLo = SUBCNode->getOperand(1);
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SDNode *MultNode = MultHi.getNode();
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unsigned MultOpc = MultHi.getOpcode();
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// MultHi and MultLo must be generated by the same node,
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if (MultLo.getNode() != MultNode)
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return false;
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// and it must be a multiplication.
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if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
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return false;
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// MultLo amd MultHi must be the first and second output of MultNode
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// respectively.
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if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
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return false;
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// Transform this to a MSUB only if SUBENode and SUBCNode are the only users
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// of the values of MultNode, in which case MultNode will be removed in later
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// phases.
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// If there exist users other than SUBENode or SUBCNode, this function returns
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// here, which will result in MultNode being mapped to a single MULT
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// instruction node rather than a pair of MULT and MSUB instructions being
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// produced.
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if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
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return false;
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DebugLoc DL = SUBENode->getDebugLoc();
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// Initialize accumulator.
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SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
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SUBCNode->getOperand(0),
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SUBENode->getOperand(0));
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// create MipsSub(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
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SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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ACCIn);
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// replace uses of sube and subc here
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if (!SDValue(SUBCNode, 0).use_empty()) {
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SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
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SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
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LoIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
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}
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if (!SDValue(SUBENode, 0).use_empty()) {
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SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
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SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
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HiIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
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}
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return true;
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}
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static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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if (DCI.isBeforeLegalize())
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return SDValue();
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if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
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selectMADD(N, &DAG))
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return SDValue(N, 0);
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return SDValue();
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}
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static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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if (DCI.isBeforeLegalize())
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return SDValue();
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if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
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selectMSUB(N, &DAG))
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return SDValue(N, 0);
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return SDValue();
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}
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SDValue
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MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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switch (N->getOpcode()) {
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case ISD::ADDE:
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return performADDECombine(N, DAG, DCI, Subtarget);
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case ISD::SUBE:
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return performSUBECombine(N, DAG, DCI, Subtarget);
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default:
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return MipsTargetLowering::PerformDAGCombine(N, DCI);
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}
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}
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MachineBasicBlock *
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MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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switch (MI->getOpcode()) {
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default:
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return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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case Mips::BPOSGE32_PSEUDO:
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return emitBPOSGE32(MI, BB);
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}
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}
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bool MipsSETargetLowering::
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isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo& FI) const {
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if (!EnableMipsTailCalls)
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return false;
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// Return false if either the callee or caller has a byval argument.
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if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
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return false;
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// Return true if the callee's argument area is no larger than the
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// caller's.
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return NextStackOffset <= FI.getIncomingArgSize();
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}
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void MipsSETargetLowering::
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
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// T9 should contain the address of the callee function if
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// -reloction-model=pic or it is an indirect call.
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if (IsPICCall || !GlobalOrExternal) {
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unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
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RegsToPass.push_front(std::make_pair(T9Reg, Callee));
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} else
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Ops.push_back(Callee);
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MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
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InternalLinkage, CLI, Callee, Chain);
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}
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SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
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bool HasLo, bool HasHi,
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SelectionDAG &DAG) const {
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EVT Ty = Op.getOperand(0).getValueType();
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DebugLoc DL = Op.getDebugLoc();
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SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
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Op.getOperand(0), Op.getOperand(1));
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SDValue Lo, Hi;
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if (HasLo)
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Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
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DAG.getConstant(Mips::sub_lo, MVT::i32));
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if (HasHi)
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Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
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DAG.getConstant(Mips::sub_hi, MVT::i32));
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if (!HasLo || !HasHi)
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return HasLo ? Lo : Hi;
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SDValue Vals[] = { Lo, Hi };
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return DAG.getMergeValues(Vals, 2, DL);
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}
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MachineBasicBlock * MipsSETargetLowering::
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emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
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// $bb:
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// bposge32_pseudo $vr0
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// =>
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// $bb:
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// bposge32 $tbb
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// $fbb:
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// li $vr2, 0
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// b $sink
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// $tbb:
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// li $vr1, 1
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// $sink:
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// $vr0 = phi($vr2, $fbb, $vr1, $tbb)
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
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DebugLoc DL = MI->getDebugLoc();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, FBB);
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F->insert(It, TBB);
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F->insert(It, Sink);
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// Transfer the remainder of BB and its successor edges to Sink.
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Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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Sink->transferSuccessorsAndUpdatePHIs(BB);
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// Add successors.
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BB->addSuccessor(FBB);
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BB->addSuccessor(TBB);
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FBB->addSuccessor(Sink);
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TBB->addSuccessor(Sink);
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// Insert the real bposge32 instruction to $BB.
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BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
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// Fill $FBB.
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unsigned VR2 = RegInfo.createVirtualRegister(RC);
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BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
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.addReg(Mips::ZERO).addImm(0);
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BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
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|
// Fill $TBB.
|
|
unsigned VR1 = RegInfo.createVirtualRegister(RC);
|
|
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
|
|
.addReg(Mips::ZERO).addImm(1);
|
|
|
|
// Insert phi function to $Sink.
|
|
BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
|
|
MI->getOperand(0).getReg())
|
|
.addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
|
|
|
|
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
|
return Sink;
|
|
}
|