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llvm-project/llvm/test/CodeGen/MIR/AMDGPU
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Jay Foad 479145a5c2 [AMDGPU] Avoid hard-coded line numbers in error message checks 
This makes it easier for us to maintain downstream changes to some of
these tests. NFC.

Differential Revision: https://reviews.llvm.org/D78716
2020-04-23 21:06:09 +01:00
..
expected-target-index-name.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
intrinsics.mir
[GISel]: Verify COPIES involving generic registers.
2018-02-09 01:27:23 +00:00
invalid-target-index-operand.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
lit.local.cfg
…
llc-target-cpu-attr-from-cmdline-ir.mir
llc: Change behavior of -mcpu with existing attribute
2020-01-07 10:10:25 -05:00
llc-target-cpu-attr-from-cmdline.mir
llc/MIR: Fix setFunctionAttributes for MIR functions
2020-01-06 17:21:51 -05:00
load-store-opt-dlc.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
machine-function-info-no-ir.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
machine-function-info-register-parse-error1.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
machine-function-info-register-parse-error2.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
machine-function-info.ll
AMDGPU: Assume f32 denormals are enabled by default
2020-04-02 17:17:12 -04:00
mfi-frame-offset-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-frame-offset-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-scratch-rsrc-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-stack-ptr-offset-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-scratch-rsrc-reg-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-stack-ptr-offset-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mir-canon-multi.mir
[MIRNamer]: Make the check lines in the test robust with regex.
2019-11-16 22:58:45 -08:00
mircanon-memoperands.mir
[llvm][MIRVRegNamerUtils] Adding hashing on memoperands.
2019-12-11 22:11:49 -05:00
parse-order-reserved-regs.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
stack-id.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
syncscopes.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
target-flags.mir
AMDGPU: Prepare for explicit absolute relocations in code generation
2019-06-16 17:43:37 +00:00
target-index-operands.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00