319 lines
11 KiB
C++
319 lines
11 KiB
C++
#include "FootCallingConvention.h"
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#include "FootISelLowering.h"
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#include "FootSubtarget.h"
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#include "MCTargetDesc/FootMCTargetDesc.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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using namespace llvm;
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FootTargetLowering::FootTargetLowering(const TargetMachine &TM,
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const FootSubtarget &STI)
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: TargetLowering(TM), Subtarget(STI) {
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addRegisterClass(MVT::i32, &Foot::GP32RegClass);
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//addRegisterClass(MVT::v2i16, &Foot::GP32RegClass);
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//addRegisterClass(MVT::v4i8, &Foot::GP32RegClass);
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setOperationAction(ISD::ADD, MVT::i32, Legal);
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setOperationAction(ISD::SUB, MVT::i32, Legal);
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setOperationAction(ISD::MUL, MVT::i32, Legal);
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setOperationAction(ISD::UDIV, MVT::i32, Legal);
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setOperationAction(ISD::UREM, MVT::i32, Legal);
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setOperationAction(ISD::SHL, MVT::i32, Legal);
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setOperationAction(ISD::ROTL, MVT::i32, Legal);
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setOperationAction(ISD::SRA, MVT::i32, Legal);
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setOperationAction(ISD::OR, MVT::i32, Legal);
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setOperationAction(ISD::AND, MVT::i32, Legal);
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setOperationAction(ISD::XOR, MVT::i32, Legal);
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setOperationAction(ISD::STORE, MVT::i32, Legal);
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setOperationAction(ISD::LOAD, MVT::i32, Legal);
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/*
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setOperationAction(ISD::ADD, MVT::v2i16, Legal);
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setOperationAction(ISD::SUB, MVT::v2i16, Legal);
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setOperationAction(ISD::MUL, MVT::v2i16, Legal);
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setOperationAction(ISD::UDIV, MVT::v2i16, Legal);
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setOperationAction(ISD::OR, MVT::v2i16, Legal);
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setOperationAction(ISD::AND, MVT::v2i16, Legal);
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setOperationAction(ISD::XOR, MVT::v2i16, Legal);
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setOperationAction(ISD::ADD, MVT::v4i8, Legal);
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setOperationAction(ISD::SUB, MVT::v4i8, Legal);
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setOperationAction(ISD::MUL, MVT::v4i8, Legal);
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setOperationAction(ISD::UDIV, MVT::v4i8, Legal);
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setOperationAction(ISD::UREM, MVT::v4i8, Legal);
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setOperationAction(ISD::OR, MVT::v4i8, Legal);
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setOperationAction(ISD::AND, MVT::v4i8, Legal);
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setOperationAction(ISD::XOR, MVT::v4i8, Legal);
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setOperationAction(ISD::FADD, MVT::f32, LibCall);
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setOperationAction(ISD::FSUB, MVT::f32, LibCall);
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setOperationAction(ISD::FMUL, MVT::f32, LibCall);
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setOperationAction(ISD::FDIV, MVT::f32, LibCall);
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setOperationAction(ISD::FREM, MVT::f32, LibCall);
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*/
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computeRegisterProperties(Subtarget.getRegisterInfo());
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}
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const char *FootTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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case FootISD::FIRST_NUMBER:
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break;
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case FootISD::CALL:
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return "FootISD::CALL";
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}
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return nullptr;
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}
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SDValue FootTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MFI.CreateFixedObject(4, 0, true);
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_Foot_Common);
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for (size_t I = 0; I < ArgLocs.size(); ++I) {
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auto &VA = ArgLocs[I];
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SDValue ArgValue;
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if (VA.isRegLoc()) {
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if (VA.getLocInfo() != CCValAssign::Full) {
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report_fatal_error("non-full passing, not yet implemented");
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}
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EVT RegVT = VA.getLocVT();
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// no special logic for selecting register class
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// just don't use one of the hardware-reserved registers
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// (which aren't part of GP32RegClass anyway)
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const TargetRegisterClass *DstRC = &Foot::GP32RegClass;
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Register VReg = RegInfo.createVirtualRegister(DstRC);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
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}
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else {
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assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
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unsigned ArgOffset = VA.getLocMemOffset();
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if (VA.getLocInfo() != CCValAssign::Full) {
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report_fatal_error("only values are supported directly in the stack");
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}
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unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
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int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
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SDValue FrameIdxNode = DAG.getFrameIndex(FrameIndex, getPointerTy(DAG.getDataLayout()));
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MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
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ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
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MVT MemVT = VA.getValVT();
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ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FrameIdxNode, PtrInfo, MemVT);
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}
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InVals.push_back(ArgValue);
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}
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return Chain;
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}
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SDValue FootTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const {
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SmallVector<CCValAssign> RetValLocs;
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MachineFunction &MF = DAG.getMachineFunction();
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CCState CCInfo(CallConv, IsVarArg, MF, RetValLocs, *DAG.getContext());
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CCInfo.AnalyzeReturn(Outs, RetCC_Foot_Common);
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SDValue Glue;
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SmallVector<SDValue> RetOps(1, Chain);
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for (size_t I = 0, E = RetValLocs.size(); I != E; ++I) {
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CCValAssign &VA = RetValLocs[I];
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assert(VA.isRegLoc() && "stack return not yet implemented");
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assert(VA.getLocInfo() == CCValAssign::Full &&
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"extension/truncation of any sort is not yet implemented");
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[I], Glue);
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// guarantee that all emitted copies are 'stuck together'
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Glue = Chain.getValue(1);
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if (Glue) {
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RetOps.push_back(Glue);
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}
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}
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SDNode *NewNode = DAG.getMachineNode(Foot::PSEUDO_RET, DL, MVT::Other, RetOps);
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return SDValue(NewNode, 0);
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}
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SDValue FootTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
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SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
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SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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CallingConv::ID CallConv = CLI.CallConv;
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MachineFunction &MF = DAG.getMachineFunction();
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SDLoc &DL = CLI.DL;
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// Tail-call optimization is not supported yet
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CLI.IsTailCall = false;
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if (CLI.IsVarArg) {
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report_fatal_error("Var args not yet implemented");
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}
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bool IsVarArg = false;
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switch (CallConv) {
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default:
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report_fatal_error("unsupported callling convention: " + Twine(CallConv));
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case CallingConv::Fast:
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case CallingConv::C:
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break;
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}
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_Foot_Common);
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unsigned NumBytes = CCInfo.getStackSize();
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for (const ISD::OutputArg &Out : Outs) {
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ISD::ArgFlagsTy OutFlags = Out.Flags;
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if (OutFlags.isByVal()) {
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report_fatal_error("Unsupported attribute");
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}
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}
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SDValue InGlue;
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auto PtrVT = getPointerTy(MF.getDataLayout());
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
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SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, Foot::RSP, getPointerTy(DAG.getDataLayout()));
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SmallVector<std::pair<Register, SDValue>> RegsToPass;
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SmallVector<SDValue, 8> MemOpChains;
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for (size_t I = 0, E = ArgLocs.size(); I != E; ++I) {
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CCValAssign &VA = ArgLocs[I];
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SDValue &Arg = OutVals[I];
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if (VA.getLocInfo() != CCValAssign::Full) {
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report_fatal_error("extensions not yet implemented: " + Twine(VA.getLocInfo()));
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}
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if (VA.isRegLoc()) {
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RegsToPass.emplace_back(VA.getLocReg(), Arg);
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continue;
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}
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assert(VA.isMemLoc() && "Expected stack argument");
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SDValue DstAddr;
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MachinePointerInfo DstInfo;
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unsigned OpSize = VA.getValVT().getSizeInBits();
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// round up to nearest byte count
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OpSize = (OpSize + 7) / 8;
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unsigned LocMemOffset = VA.getLocMemOffset();
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SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, DL);
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// pointer arithmetic
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DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
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DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
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SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo);
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MemOpChains.push_back(Store);
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}
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if (!MemOpChains.empty()) {
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Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
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}
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for (auto& RegToPass : RegsToPass) {
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Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first, RegToPass.second, InGlue);
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InGlue = Chain.getValue(1);
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}
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, G->getOffset(), 0);
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}
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
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}
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else {
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report_fatal_error("Other calls not supported");
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}
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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for (auto &Reg : RegsToPass) {
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Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
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}
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const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
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const uint32_t *Mask = TRI.getCallPreservedMask(MF, CallConv);
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assert(Mask && "Missing call preserved mask for calling convention");
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Ops.push_back(DAG.getRegisterMask(Mask));
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if (InGlue.getNode()) {
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Ops.push_back(InGlue);
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}
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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Chain = DAG.getNode(FootISD::CALL, DL, NodeTys, Ops);
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InGlue = Chain.getValue(1);
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DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
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Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InGlue, DL);
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InGlue = Chain.getValue(1);
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SmallVector<CCValAssign, 16> RetValLocs;
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CCState CCRetInfo(CallConv, IsVarArg, MF, RetValLocs, *DAG.getContext());
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CCRetInfo.AnalyzeCallResult(Ins, RetCC_Foot_Common);
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for (size_t I = 0, E = RetValLocs.size(); I != E; ++I) {
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CCValAssign &VA = RetValLocs[I];
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assert(VA.isRegLoc() && "stack return not yet implemented");
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assert(VA.getLocInfo() == CCValAssign::Full && "extension/truncation not yet implemented");
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Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getValVT(), InGlue)
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.getValue(1);
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InGlue = Chain.getValue(2);
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InVals.push_back(Chain.getValue(0));
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}
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return Chain;
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}
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bool FootTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
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const Type *RetTy) const {
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
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MF.getFunction().getContext());
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return !IsVarArg && CCInfo.CheckReturn(Outs, RetCC_Foot_Common);
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}
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