84abec2855
The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
28 lines
956 B
LLVM
28 lines
956 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
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; FIXME: This test has a fatal error in 32-bit mode
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@fsc128 = external global fp128
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define void @atomic_fetch_swapf128(fp128 %x) nounwind {
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; CHECK-LABEL: atomic_fetch_swapf128:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: movq %rsi, %rcx
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: movq _fsc128@{{.*}}(%rip), %rsi
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; CHECK-NEXT: movq (%rsi), %rax
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; CHECK-NEXT: movq 8(%rsi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB0_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lock cmpxchg16b (%rsi)
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; CHECK-NEXT: jne LBB0_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%t1 = atomicrmw xchg fp128* @fsc128, fp128 %x acquire
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ret void
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}
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