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Xing GUO 013e17f50e [ARM][MC] Update one test case in 'test/MC/Disassembler/ARM/invalid-armv7.txt' 
Summary:
Instruction `[0xfe 0xf0 0x20 0xe3]` is a valid instruction on ARM-v7, which is `dbg #14`. See: 
https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/ARMv7-A-R-manual.pdf 
(Page: 377)

```
Encoding A1:
DBG<c> #<option>

|31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16|15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00|
|      cond | 0  0  1  1  0| 0| 1  0| 0  0  0  0| 1  1  1  1| 0  0  0  0| 1  1  1  1|    option |
```

Reviewers: fhahn, efriedma

Reviewed By: efriedma

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58873

llvm-svn: 355374
2019-03-05 03:07:56 +00:00
..
addrmode2-reencoding.txt
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arm-LDREXD-reencoding.txt
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arm-STREXD-reencoding.txt
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arm-tests.txt
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arm-thumb-trustzone.txt
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arm-trustzone.txt
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arm-vmrs_vmsr.txt
[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
2017-10-18 14:47:37 +00:00
armv8.1a.txt
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armv8.2a-dotprod-a32.s
[ARM] Assembler support for the ARMv8.2a dot product instructions
2017-08-11 09:52:30 +00:00
armv8.2a-dotprod-t32.s
[ARM] Assembler support for the ARMv8.2a dot product instructions
2017-08-11 09:52:30 +00:00
armv8.3a-js-arm.txt
[ARM][AArch64] v8.3-A Javascript Conversion
2017-08-22 11:08:21 +00:00
armv8.3a-js-thumb.txt
[ARM][AArch64] v8.3-A Javascript Conversion
2017-08-22 11:08:21 +00:00
armv8.4a-trace-a32.txt
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction
2018-07-06 08:03:12 +00:00
armv8.4a-trace-t32.txt
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction
2018-07-06 08:03:12 +00:00
armv8.5a-sb-thumb.txt
[ARM] Add command-line option for SB
2019-01-03 12:09:12 +00:00
armv8.5a-sb.txt
[NFC] Fix missing testfile change of rL350299
2019-01-03 12:48:06 +00:00
armv8a-fpmul-a32.txt
[ARM/AArch64] Support FP16 +fp16fml instructions
2018-08-17 11:29:49 +00:00
armv8a-fpmul-t32.txt
[ARM/AArch64] Support FP16 +fp16fml instructions
2018-08-17 11:29:49 +00:00
basic-arm-instructions-v8.txt
…
basic-arm-instructions.txt
[ARM][v8.5A] Add speculation barriers SSBB and PSSBB
2018-09-28 08:27:56 +00:00
crc32-thumb.txt
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crc32.txt
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csdb-arm.txt
[ARM][AArch64] Add CSDB speculation barrier instruction
2018-02-06 09:24:47 +00:00
csdb-thumb.txt
[ARM][AArch64] Add CSDB speculation barrier instruction
2018-02-06 09:24:47 +00:00
d16.txt
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dfb-arm.txt
[ARM] Armv8-R DFB instruction
2017-12-21 11:17:49 +00:00
dfb-thumb.txt
[ARM] Armv8-R DFB instruction
2017-12-21 11:17:49 +00:00
fp-armv8.txt
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fp-encoding.txt
Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR"
2017-08-08 17:16:46 +00:00
fullfp16-arm-neg.txt
[ARM] Add ARMv8.2-A FP16 scalar instructions
2016-01-25 10:26:26 +00:00
fullfp16-arm-nopred.txt
[ARM] Make fullfp16 instructions not conditionalisable.
2019-02-25 10:39:53 +00:00
fullfp16-arm.txt
[ARM] Add ARMv8.2-A FP16 scalar instructions
2016-01-25 10:26:26 +00:00
fullfp16-neon-arm-neg.txt
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fullfp16-neon-arm.txt
…
fullfp16-neon-thumb-neg.txt
…
fullfp16-neon-thumb.txt
…
fullfp16-thumb-neg.txt
[ARM] Add ARMv8.2-A FP16 scalar instructions
2016-01-25 10:26:26 +00:00
fullfp16-thumb-nopred.txt
[ARM] Make fullfp16 instructions not conditionalisable.
2019-02-25 10:39:53 +00:00
fullfp16-thumb.txt
[ARM] Add ARMv8.2-A FP16 scalar instructions
2016-01-25 10:26:26 +00:00
hex-immediates.txt
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invalid-armv7.txt
[ARM][MC] Update one test case in 'test/MC/Disassembler/ARM/invalid-armv7.txt'
2019-03-05 03:07:56 +00:00
invalid-armv8.1a.txt
…
invalid-armv8.txt
…
invalid-because-armv7.txt
…
invalid-FSTMX-arm.txt
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invalid-IT-CC15.txt
ARM: correctly decode VFP instructions following unpredictable t2IT
2018-06-26 11:39:20 +00:00
invalid-thumb-MSR-MClass.txt
[ARM]Decoding MSR with unpredictable destination register causes an assert
2018-03-06 15:21:19 +00:00
invalid-thumbv7-xfail.txt
…
invalid-thumbv7.txt
[ARM] Re-commit r324600 with fixed LLVMBuild.txt
2018-02-08 14:31:22 +00:00
invalid-thumbv8.1a.txt
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invalid-thumbv8.txt
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invalid-virtexts.arm.txt
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ldrd-armv4.txt
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lit.local.cfg
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load-store-acquire-release-v8-thumb.txt
…
load-store-acquire-release-v8.txt
…
marked-up-thumb.txt
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memory-arm-instructions.txt
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move-banked-regs-arm.txt
…
move-banked-regs-thumb.txt
…
neon-complex-arm.txt
[ARM] v8.3-a complex number support
2017-09-29 13:11:33 +00:00
neon-complex-thumb.txt
[ARM] v8.3-a complex number support
2017-09-29 13:11:33 +00:00
neon-crypto.txt
…
neon-tests.txt
…
neon-v8.txt
…
neon.txt
…
neont2.txt
…
neont-VLD-reencoding.txt
…
neont-VST-reencoding.txt
…
ras-extension-arm.txt
RAS extensions are part of ARMv8.2-A. This change enables them by introducing a
2016-06-03 14:03:27 +00:00
ras-extension-thumb.txt
RAS extensions are part of ARMv8.2-A. This change enables them by introducing a
2016-06-03 14:03:27 +00:00
thumb1.txt
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thumb2-preloads.txt
…
thumb2-v8.txt
…
thumb2-v8m.txt
[ARM] Add new system registers to ARMv8-M Baseline/Mainline
2016-01-25 11:25:36 +00:00
thumb2.txt
[ARM][v8.5A] Add speculation barriers SSBB and PSSBB
2018-09-28 08:27:56 +00:00
thumb-fp-armv8.txt
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thumb-MSR-MClass.txt
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thumb-neon-crypto.txt
…
thumb-neon-v8.txt
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thumb-printf.txt
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thumb-tests.txt
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thumb-v8.1a.txt
…
thumb-v8.txt
…
thumb-vmrs_vmsr.txt
[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
2017-10-18 14:47:37 +00:00
unpredictable-ADC-arm.txt
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unpredictable-ADDREXT3-arm.txt
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unpredictable-AExtI-arm.txt
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unpredictable-AI1cmp-arm.txt
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unpredictable-BFI.txt
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unpredictable-LDR-arm.txt
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unpredictable-LDRD-arm.txt
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unpredictable-LSL-regform.txt
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unpredictable-MRRC2-arm.txt
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unpredictable-MRS-arm.txt
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unpredictable-MUL-arm.txt
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unpredictable-MVN-arm.txt
[ARM] Add support for unpredictable MVN instructions.
2018-02-01 12:06:57 +00:00
unpredictable-RSC-arm.txt
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unpredictable-SEL-arm.txt
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unpredictable-SHADD16-arm.txt
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unpredictable-SSAT-arm.txt
[ARM] Saturation instructions are DSP-only
2016-07-25 22:25:25 +00:00
unpredictable-STRBrs-arm.txt
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unpredictable-swp-arm.txt
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unpredictable-UQADD8-arm.txt
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unpredictables-thumb.txt
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vfp4.txt
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virtexts-arm.txt
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virtexts-thumb.txt
…