2aaba44b5c
The Linux kernel build uses absolute expressions suffixed with @lo/@ha relocations. This currently doesn't work for DS/DQ form instructions and there is no reason for it not to. It also works with GAS. This patch allows this as long as the value is a multiple of 4/16 for DS/DQ form. Differential revision: https://reviews.llvm.org/D115419
66 lines
2.0 KiB
C++
66 lines
2.0 KiB
C++
//===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCFIXUPKINDS_H
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#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCFIXUPKINDS_H
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#include "llvm/MC/MCFixup.h"
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#undef PPC
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namespace llvm {
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namespace PPC {
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enum Fixups {
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// 24-bit PC relative relocation for direct branches like 'b' and 'bl'.
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fixup_ppc_br24 = FirstTargetFixupKind,
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// 24-bit PC relative relocation for direct branches like 'b' and 'bl' where
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// the caller does not use the TOC.
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fixup_ppc_br24_notoc,
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/// 14-bit PC relative relocation for conditional branches.
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fixup_ppc_brcond14,
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/// 24-bit absolute relocation for direct branches like 'ba' and 'bla'.
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fixup_ppc_br24abs,
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/// 14-bit absolute relocation for conditional branches.
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fixup_ppc_brcond14abs,
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/// A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like
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/// 'li' or 'addis'.
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fixup_ppc_half16,
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/// A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for
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/// instrs like 'std'.
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fixup_ppc_half16ds,
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// A 34-bit fixup corresponding to PC-relative paddi.
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fixup_ppc_pcrel34,
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// A 34-bit fixup corresponding to Non-PC-relative paddi.
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fixup_ppc_imm34,
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/// Not a true fixup, but ties a symbol to a call to __tls_get_addr for the
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/// TLS general and local dynamic models, or inserts the thread-pointer
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/// register number.
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fixup_ppc_nofixup,
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/// A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for
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/// instrs like 'lxv'. Produces the same relocation as fixup_ppc_half16ds.
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fixup_ppc_half16dq,
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// Marker
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LastTargetFixupKind,
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NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
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};
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}
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}
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#endif
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