fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
54 lines
2.1 KiB
LLVM
54 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4:
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; GCN: s_load_dwordx2
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v2i32_as_v4i16_align_4(ptr addrspace(3) align 4 %out, <2 x i32> %x) #0 {
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%x.bc = bitcast <2 x i32> %x to <4 x i16>
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store <4 x i16> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v4i32_as_v8i16_align_4:
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; GCN: s_load_dwordx4
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v4i32_as_v8i16_align_4(ptr addrspace(3) align 4 %out, <4 x i32> %x) #0 {
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%x.bc = bitcast <4 x i32> %x to <8 x i16>
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store <8 x i16> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v2i32_as_i64_align_4:
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; GCN: s_load_dwordx2
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v2i32_as_i64_align_4(ptr addrspace(3) align 4 %out, <2 x i32> %x) #0 {
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%x.bc = bitcast <2 x i32> %x to <4 x i16>
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store <4 x i16> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v4i32_as_v2i64_align_4:
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; GCN: s_load_dwordx4
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v4i32_as_v2i64_align_4(ptr addrspace(3) align 4 %out, <4 x i32> %x) #0 {
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%x.bc = bitcast <4 x i32> %x to <2 x i64>
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store <2 x i64> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v4i16_as_v2i32_align_4:
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; GCN: s_load_dword s
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; GCN-NEXT: s_load_dwordx2 s
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; GCN-NOT: {{buffer|flat|global}}
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v4i16_as_v2i32_align_4(ptr addrspace(3) align 4 %out, <4 x i16> %x) #0 {
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%x.bc = bitcast <4 x i16> %x to <2 x i32>
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store <2 x i32> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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