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llvm-project/llvm/test/CodeGen
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David Green ad12e6ee95 [ARM] Turn sext_inreg(VGetLaneu) into VGetLaneu 
This adds a DAG combine for converting sext_inreg of VGetLaneu into
VGetLanes, providing the types match correctly.

Differential Revision: https://reviews.llvm.org/D95073
2021-02-01 11:10:35 +00:00
..
AArch64
[ExpandMemCmpPass] Preserve Dominator Tree, if available
2021-01-30 01:14:51 +03:00
AMDGPU
RegAlloc: Fix assert if all registers in class reserved
2021-01-31 11:10:04 -05:00
ARC
…
ARM
[ARM] Turn sext_inreg(VGetLaneu) into VGetLaneu
2021-02-01 11:10:35 +00:00
AVR
[AVR] Optimize 16-bit int shift
2021-01-28 15:10:11 +08:00
BPF
[BPF] support atomic instructions
2020-12-03 07:38:00 -08:00
Generic
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
Hexagon
[NewPM][opt] Run the "default" AA pipeline by default
2021-01-21 21:08:54 -08:00
Inputs
…
Lanai
…
Mips
[CodeGen] Try to make the print of memory operand alignment a little more user friendly.
2021-01-11 19:58:47 -08:00
MIR
[AMDGPU] Implement mir parseCustomPseudoSourceValue
2021-01-22 11:24:08 +01:00
MSP430
…
NVPTX
[NFC] Disallow unused prefixes under llvm/test/CodeGen
2021-01-11 12:32:18 -08:00
PowerPC
[PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases
2021-01-28 15:17:32 -05:00
RISCV
[RISCV][LegalizeTypes] Try to expand BSWAP before promoting if the promoted BSWAP would expand anyway.
2021-01-31 14:33:29 -08:00
SPARC
[SPARC] Fix fp128 load/stores
2021-01-13 14:59:50 -08:00
SystemZ
[SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds
2021-01-14 15:46:27 +00:00
Thumb
[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer
2021-01-23 09:10:03 +00:00
Thumb2
[ARM] Turn sext_inreg(VGetLaneu) into VGetLaneu
2021-02-01 11:10:35 +00:00
VE
[VE] Update VELIntrinsic tests
2021-01-13 00:12:50 +09:00
WebAssembly
[WebAssembly] Prototype i8x16 to i32x4 widening instructions
2021-01-28 10:59:32 -08:00
WinCFGuard
…
WinEH
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X86
[X86][AVX] combineExtractWithShuffle - combine extracts from 256/512-bit vector shuffles.
2021-02-01 10:31:43 +00:00
XCore
[test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:47:16 -08:00