ad39049ec4
Almost all of the rotate idioms that are valid for an 'or' are also valid when the halves are combined with an 'add'. Further, many of these cases are not handled by common bits tracking meaning that the 'add' is not converted to a 'disjoint or'.
201 lines
5.4 KiB
LLVM
201 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
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target triple = "nvptx64-nvidia-cuda"
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define i32 @test_simple_rotl(i32 %x) {
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; CHECK-LABEL: test_simple_rotl:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror r0, r0, #25
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; CHECK-NEXT: bx lr
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%shl = shl i32 %x, 7
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%shr = lshr i32 %x, 25
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%add = add i32 %shl, %shr
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ret i32 %add
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}
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define i32 @test_simple_rotr(i32 %x) {
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; CHECK-LABEL: test_simple_rotr:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror r0, r0, #7
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; CHECK-NEXT: bx lr
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%shr = lshr i32 %x, 7
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%shl = shl i32 %x, 25
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%add = add i32 %shr, %shl
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ret i32 %add
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}
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define i32 @test_rotl_var(i32 %x, i32 %y) {
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; CHECK-LABEL: test_rotl_var:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r1, r1, #32
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; CHECK-NEXT: ror r0, r0, r1
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; CHECK-NEXT: bx lr
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%shl = shl i32 %x, %y
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%sub = sub i32 32, %y
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%shr = lshr i32 %x, %sub
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%add = add i32 %shl, %shr
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ret i32 %add
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}
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define i32 @test_rotr_var(i32 %x, i32 %y) {
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; CHECK-LABEL: test_rotr_var:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror r0, r0, r1
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; CHECK-NEXT: bx lr
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%shr = lshr i32 %x, %y
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%sub = sub i32 32, %y
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%shl = shl i32 %x, %sub
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%add = add i32 %shr, %shl
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ret i32 %add
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}
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define i32 @test_invalid_rotl_var_and(i32 %x, i32 %y) {
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; CHECK-LABEL: test_invalid_rotl_var_and:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r2, r1, #0
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; CHECK-NEXT: and r2, r2, #31
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; CHECK-NEXT: lsr r2, r0, r2
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; CHECK-NEXT: add r0, r2, r0, lsl r1
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; CHECK-NEXT: bx lr
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%shr = shl i32 %x, %y
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%sub = sub nsw i32 0, %y
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%and = and i32 %sub, 31
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%shl = lshr i32 %x, %and
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%add = add i32 %shl, %shr
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ret i32 %add
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}
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define i32 @test_invalid_rotr_var_and(i32 %x, i32 %y) {
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; CHECK-LABEL: test_invalid_rotr_var_and:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsr r2, r0, r1
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; CHECK-NEXT: rsb r1, r1, #0
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; CHECK-NEXT: and r1, r1, #31
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; CHECK-NEXT: add r0, r2, r0, lsl r1
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; CHECK-NEXT: bx lr
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%shr = lshr i32 %x, %y
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%sub = sub nsw i32 0, %y
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%and = and i32 %sub, 31
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%shl = shl i32 %x, %and
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%add = add i32 %shr, %shl
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ret i32 %add
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}
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define i32 @test_fshl_special_case(i32 %x0, i32 %x1, i32 %y) {
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; CHECK-LABEL: test_fshl_special_case:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsl r0, r0, r2
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; CHECK-NEXT: eor r2, r2, #31
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; CHECK-NEXT: lsr r1, r1, #1
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; CHECK-NEXT: add r0, r0, r1, lsr r2
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; CHECK-NEXT: bx lr
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%shl = shl i32 %x0, %y
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%srli = lshr i32 %x1, 1
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%x = xor i32 %y, 31
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%srlo = lshr i32 %srli, %x
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%o = add i32 %shl, %srlo
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ret i32 %o
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}
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define i32 @test_fshr_special_case(i32 %x0, i32 %x1, i32 %y) {
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; CHECK-LABEL: test_fshr_special_case:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsr r1, r1, r2
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; CHECK-NEXT: eor r2, r2, #31
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; CHECK-NEXT: lsl r0, r0, #1
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; CHECK-NEXT: add r0, r1, r0, lsl r2
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; CHECK-NEXT: bx lr
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%shl = lshr i32 %x1, %y
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%srli = shl i32 %x0, 1
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%x = xor i32 %y, 31
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%srlo = shl i32 %srli, %x
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%o = add i32 %shl, %srlo
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ret i32 %o
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}
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define i64 @test_rotl_udiv_special_case(i64 %i) {
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; CHECK-LABEL: test_rotl_udiv_special_case:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: adds r2, r0, r1
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; CHECK-NEXT: ldr r12, .LCPI8_0
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; CHECK-NEXT: adc lr, r2, #0
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; CHECK-NEXT: umull r3, r2, lr, r12
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; CHECK-NEXT: bic r3, r2, #1
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; CHECK-NEXT: add r2, r3, r2, lsr #1
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; CHECK-NEXT: ldr r3, .LCPI8_1
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; CHECK-NEXT: sub r2, lr, r2
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbc r1, r1, #0
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; CHECK-NEXT: umull r2, lr, r0, r12
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; CHECK-NEXT: mla r0, r0, r3, lr
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; CHECK-NEXT: mla r0, r1, r12, r0
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; CHECK-NEXT: lsl r1, r2, #28
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; CHECK-NEXT: orr r1, r1, r0, lsr #4
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; CHECK-NEXT: lsl r0, r0, #28
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; CHECK-NEXT: orr r0, r0, r2, lsr #4
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; CHECK-NEXT: pop {r11, pc}
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI8_0:
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; CHECK-NEXT: .long 2863311531 @ 0xaaaaaaab
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; CHECK-NEXT: .LCPI8_1:
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; CHECK-NEXT: .long 2863311530 @ 0xaaaaaaaa
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%lhs_div = udiv i64 %i, 3
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%rhs_div = udiv i64 %i, 48
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%lhs_shift = shl i64 %lhs_div, 60
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%out = add i64 %lhs_shift, %rhs_div
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ret i64 %out
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}
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define i32 @test_rotl_mul_special_case(i32 %i) {
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; CHECK-LABEL: test_rotl_mul_special_case:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: add r0, r0, r0, lsl #3
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; CHECK-NEXT: ror r0, r0, #25
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; CHECK-NEXT: bx lr
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%lhs_mul = mul i32 %i, 9
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%rhs_mul = mul i32 %i, 1152
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%lhs_shift = lshr i32 %lhs_mul, 25
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%out = add i32 %lhs_shift, %rhs_mul
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ret i32 %out
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}
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define i64 @test_rotl_mul_with_mask_special_case(i64 %i) {
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; CHECK-LABEL: test_rotl_mul_with_mask_special_case:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #9
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; CHECK-NEXT: add r1, r1, r1, lsl #3
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; CHECK-NEXT: umull r2, r3, r0, r2
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; CHECK-NEXT: and r0, r0, #1
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; CHECK-NEXT: lsl r0, r0, #7
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; CHECK-NEXT: add r1, r3, r1
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; CHECK-NEXT: orr r0, r0, r1, lsr #25
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; CHECK-NEXT: mov r1, #0
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; CHECK-NEXT: bx lr
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%lhs_mul = mul i64 %i, 1152
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%rhs_mul = mul i64 %i, 9
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%lhs_and = and i64 %lhs_mul, 160
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%rhs_shift = lshr i64 %rhs_mul, 57
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%out = add i64 %lhs_and, %rhs_shift
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ret i64 %out
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}
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define i32 @test_fshl_with_mask_special_case(i32 %x) {
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; CHECK-LABEL: test_fshl_with_mask_special_case:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #32
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; CHECK-NEXT: orr r0, r1, r0, ror #27
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; CHECK-NEXT: bic r0, r0, #30
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; CHECK-NEXT: bx lr
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%or1 = or i32 %x, 1
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%sh1 = shl i32 %or1, 5
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%sh2 = lshr i32 %x, 27
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%1 = and i32 %sh2, 1
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%r = add i32 %sh1, %1
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ret i32 %r
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}
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