00ecf67045
For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure llvm-svn: 360505
115 lines
3.8 KiB
C++
115 lines
3.8 KiB
C++
//===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an RISCV MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstPrinter.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "Utils/RISCVBaseInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "RISCVGenAsmWriter.inc"
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// Include the auto-generated portion of the compress emitter.
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#define GEN_UNCOMPRESS_INSTR
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#include "RISCVGenCompressInstEmitter.inc"
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static cl::opt<bool>
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NoAliases("riscv-no-aliases",
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cl::desc("Disable the emission of assembler pseudo instructions"),
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cl::init(false), cl::Hidden);
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void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot, const MCSubtargetInfo &STI) {
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bool Res = false;
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const MCInst *NewMI = MI;
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MCInst UncompressedMI;
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if (!NoAliases)
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Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
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if (Res)
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NewMI = const_cast<MCInst *>(&UncompressedMI);
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if (NoAliases || !printAliasInstr(NewMI, STI, O))
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printInstruction(NewMI, STI, O);
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printAnnotation(O, Annot);
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}
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void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
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O << getRegisterName(RegNo);
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}
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void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O,
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const char *Modifier) {
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assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
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const MCOperand &MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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printRegName(O, MO.getReg());
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return;
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}
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if (MO.isImm()) {
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O << MO.getImm();
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return;
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}
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assert(MO.isExpr() && "Unknown operand kind in printOperand");
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MO.getExpr()->print(O, &MAI);
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}
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void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNo).getImm();
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auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
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if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
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O << SysReg->Name;
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else
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O << Imm;
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}
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void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned FenceArg = MI->getOperand(OpNo).getImm();
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assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
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if ((FenceArg & RISCVFenceField::I) != 0)
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O << 'i';
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if ((FenceArg & RISCVFenceField::O) != 0)
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O << 'o';
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if ((FenceArg & RISCVFenceField::R) != 0)
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O << 'r';
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if ((FenceArg & RISCVFenceField::W) != 0)
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O << 'w';
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if (FenceArg == 0)
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O << "unknown";
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}
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void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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auto FRMArg =
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static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
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O << RISCVFPRndMode::roundingModeToString(FRMArg);
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}
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