9ab812d475
Summary: This fixes a hardware bug that makes a branch offset of 0x3f unsafe. This replaces the 32 bit branch with offset 0x3f to a 64 bit instruction that includes the same 32 bit branch and the encoding for a s_nop 0 to follow. The relaxer than modifies the offsets accordingly. Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63494 llvm-svn: 364451
75 lines
1.1 KiB
ArmAsm
75 lines
1.1 KiB
ArmAsm
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
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s_getpc_b64 s[0:1]
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s_cbranch_vccnz BB0_1
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// GFX10: s_cbranch_vccnz BB0_1 ; encoding: [A,A,0x87,0xbf]
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// GFX10-NEXT: ; fixup A - offset: 0, value: BB0_1, kind: fixup_si_sopp_br
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// BIN: s_cbranch_vccnz BB0_1 // 000000000004: BF870040
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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BB0_1:
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s_nop 0
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s_endpgm
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