addbf732c8
We use a SmallString<512> and attempted to reserve enough space for CPU plus Features, but that doesn't account for all the things that get added to the string. Reorder the string so the shortest things go first which shouldn't exceed the small size. Finally add the feature string at the end which might be long. This should ensure at most one heap allocation without needing to use reserve. I don't know if this matters much in practice, but I was looking into something else that will require more code here and noticed the odd reserve call.
564 lines
19 KiB
C++
564 lines
19 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "TargetInfo/X86TargetInfo.h"
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#include "X86.h"
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#include "X86CallLowering.h"
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#include "X86LegalizerInfo.h"
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#include "X86MacroFusion.h"
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#include "X86Subtarget.h"
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#include "X86TargetObjectFile.h"
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#include "X86TargetTransformInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/ExecutionDomainFix.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/CFGuard.h"
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#include <memory>
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#include <string>
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using namespace llvm;
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static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
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cl::desc("Enable the machine combiner pass"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
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cl::desc("Enable the conditional branch "
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"folding pass"),
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cl::init(false), cl::Hidden);
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
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// Register the target.
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RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
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RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeGlobalISel(PR);
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initializeWinEHStatePassPass(PR);
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initializeFixupBWInstPassPass(PR);
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initializeEvexToVexInstPassPass(PR);
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initializeFixupLEAPassPass(PR);
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initializeFPSPass(PR);
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initializeX86FixupSetCCPassPass(PR);
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initializeX86CallFrameOptimizationPass(PR);
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initializeX86CmovConverterPassPass(PR);
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initializeX86ExpandPseudoPass(PR);
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initializeX86ExecutionDomainFixPass(PR);
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initializeX86DomainReassignmentPass(PR);
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initializeX86AvoidSFBPassPass(PR);
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initializeX86AvoidTrailingCallPassPass(PR);
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initializeX86SpeculativeLoadHardeningPassPass(PR);
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initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
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initializeX86FlagsCopyLoweringPassPass(PR);
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initializeX86CondBrFoldingPassPass(PR);
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initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
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initializeX86LoadValueInjectionRetHardeningPassPass(PR);
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initializeX86OptimizeLEAPassPass(PR);
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initializeX86PartialReductionPass(PR);
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatMachO()) {
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if (TT.getArch() == Triple::x86_64)
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return std::make_unique<X86_64MachoTargetObjectFile>();
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return std::make_unique<TargetLoweringObjectFileMachO>();
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}
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if (TT.isOSBinFormatCOFF())
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return std::make_unique<TargetLoweringObjectFileCOFF>();
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return std::make_unique<X86ELFTargetObjectFile>();
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}
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static std::string computeDataLayout(const Triple &TT) {
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// X86 is little endian
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std::string Ret = "e";
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Ret += DataLayout::getManglingComponent(TT);
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// X86 and x32 have 32 bit pointers.
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if ((TT.isArch64Bit() &&
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(TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
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!TT.isArch64Bit())
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Ret += "-p:32:32";
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// Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
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Ret += "-p270:32:32-p271:32:32-p272:64:64";
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// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
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if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
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Ret += "-i64:64";
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else if (TT.isOSIAMCU())
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Ret += "-i64:32-f64:32";
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else
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Ret += "-f64:32:64";
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// Some ABIs align long double to 128 bits, others to 32.
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if (TT.isOSNaCl() || TT.isOSIAMCU())
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; // No f80
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else if (TT.isArch64Bit() || TT.isOSDarwin())
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Ret += "-f80:128";
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else
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Ret += "-f80:32";
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if (TT.isOSIAMCU())
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Ret += "-f128:32";
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// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
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if (TT.isArch64Bit())
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Ret += "-n8:16:32:64";
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else
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Ret += "-n8:16:32";
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// The stack is aligned to 32 bits on some ABIs and 128 bits on others.
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if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
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Ret += "-a:0:32-S32";
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else
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Ret += "-S128";
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return Ret;
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}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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bool JIT,
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Optional<Reloc::Model> RM) {
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bool is64Bit = TT.getArch() == Triple::x86_64;
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if (!RM.hasValue()) {
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// JIT codegen should use static relocations by default, since it's
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// typically executed in process and not relocatable.
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if (JIT)
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return Reloc::Static;
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// Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
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// Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
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// use static relocation model by default.
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if (TT.isOSDarwin()) {
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if (is64Bit)
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return Reloc::PIC_;
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return Reloc::DynamicNoPIC;
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}
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if (TT.isOSWindows() && is64Bit)
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return Reloc::PIC_;
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return Reloc::Static;
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}
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// ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
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// is defined as a model for code which may be used in static or dynamic
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// executables but not necessarily a shared library. On X86-32 we just
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// compile in -static mode, in x86-64 we use PIC.
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if (*RM == Reloc::DynamicNoPIC) {
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if (is64Bit)
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return Reloc::PIC_;
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if (!TT.isOSDarwin())
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return Reloc::Static;
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}
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// If we are on Darwin, disallow static relocation model in X86-64 mode, since
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// the Mach-O file format doesn't support it.
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if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
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return Reloc::PIC_;
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return *RM;
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}
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static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
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bool JIT, bool Is64Bit) {
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if (CM) {
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if (*CM == CodeModel::Tiny)
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report_fatal_error("Target does not support the tiny CodeModel", false);
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return *CM;
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}
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if (JIT)
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return Is64Bit ? CodeModel::Large : CodeModel::Small;
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return CodeModel::Small;
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}
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/// Create an X86 target.
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///
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X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(
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T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(TT, JIT, RM),
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getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
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OL),
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TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
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// On PS4, the "return address" of a 'noreturn' call must still be within
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// the calling function, and TrapUnreachable is an easy way to get that.
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if (TT.isPS4() || TT.isOSBinFormatMachO()) {
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this->Options.TrapUnreachable = true;
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this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
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}
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setMachineOutliner(true);
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// x86 supports the debug entry values.
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setSupportsDebugEntryValues(true);
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initAsmInfo();
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}
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X86TargetMachine::~X86TargetMachine() = default;
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const X86Subtarget *
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X86TargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString()
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: (StringRef)TargetCPU;
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StringRef FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString()
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: (StringRef)TargetFS;
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SmallString<512> Key;
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// The additions here are ordered so that the definitely short strings are
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// added first so we won't exceed the small size. We append the
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// much longer FS string at the end so that we only heap allocate at most
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// one time.
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// Extract prefer-vector-width attribute.
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unsigned PreferVectorWidthOverride = 0;
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if (F.hasFnAttribute("prefer-vector-width")) {
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StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
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unsigned Width;
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if (!Val.getAsInteger(0, Width)) {
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Key += "prefer-vector-width=";
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Key += Val;
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PreferVectorWidthOverride = Width;
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}
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}
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// Extract min-legal-vector-width attribute.
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unsigned RequiredVectorWidth = UINT32_MAX;
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if (F.hasFnAttribute("min-legal-vector-width")) {
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StringRef Val =
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F.getFnAttribute("min-legal-vector-width").getValueAsString();
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unsigned Width;
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if (!Val.getAsInteger(0, Width)) {
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Key += "min-legal-vector-width=";
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Key += Val;
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RequiredVectorWidth = Width;
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}
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}
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// Add CPU to the Key.
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Key += CPU;
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// Keep track of the start of the feature portion of the string.
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unsigned FSStart = Key.size();
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function before we can generate a subtarget. We also need to use
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// it as a key for the subtarget since that can be the only difference
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// between two functions.
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bool SoftFloat =
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F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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// If the soft float attribute is set on the function turn on the soft float
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// subtarget feature.
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if (SoftFloat)
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Key += FS.empty() ? "+soft-float" : "+soft-float,";
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Key += FS;
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// We may have added +soft-float to the features so move the StringRef to
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// point to the full string in the Key.
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FS = Key.substr(FSStart);
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auto &I = SubtargetMap[Key];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = std::make_unique<X86Subtarget>(
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TargetTriple, CPU, FS, *this,
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MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
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RequiredVectorWidth);
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}
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return I.get();
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}
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//===----------------------------------------------------------------------===//
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// X86 TTI query.
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//===----------------------------------------------------------------------===//
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TargetTransformInfo
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X86TargetMachine::getTargetTransformInfo(const Function &F) {
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return TargetTransformInfo(X86TTIImpl(this, F));
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86 Code Generator Pass Configuration Options.
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class X86PassConfig : public TargetPassConfig {
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public:
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X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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X86TargetMachine &getX86TargetMachine() const {
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return getTM<X86TargetMachine>();
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}
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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ScheduleDAGMILive *DAG = createGenericSchedLive(C);
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DAG->addMutation(createX86MacroFusionDAGMutation());
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return DAG;
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}
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ScheduleDAGInstrs *
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createPostMachineScheduler(MachineSchedContext *C) const override {
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ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
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DAG->addMutation(createX86MacroFusionDAGMutation());
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return DAG;
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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bool addIRTranslator() override;
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bool addLegalizeMachineIR() override;
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bool addRegBankSelect() override;
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bool addGlobalInstructionSelect() override;
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bool addILPOpts() override;
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bool addPreISel() override;
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void addMachineSSAOptimization() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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void addPreEmitPass() override;
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void addPreEmitPass2() override;
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void addPreSched2() override;
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std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
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};
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class X86ExecutionDomainFix : public ExecutionDomainFix {
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public:
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static char ID;
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X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
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StringRef getPassName() const override {
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return "X86 Execution Dependency Fix";
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}
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};
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char X86ExecutionDomainFix::ID;
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
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"X86 Execution Domain Fix", false, false)
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INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
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INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
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"X86 Execution Domain Fix", false, false)
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TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new X86PassConfig(*this, PM);
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}
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void X86PassConfig::addIRPasses() {
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addPass(createAtomicExpandPass());
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TargetPassConfig::addIRPasses();
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if (TM->getOptLevel() != CodeGenOpt::None) {
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addPass(createInterleavedAccessPass());
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addPass(createX86PartialReductionPass());
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}
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// Add passes that handle indirect branch removal and insertion of a retpoline
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// thunk. These will be a no-op unless a function subtarget has the retpoline
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// feature enabled.
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addPass(createIndirectBrExpandPass());
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// Add Control Flow Guard checks.
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const Triple &TT = TM->getTargetTriple();
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if (TT.isOSWindows()) {
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if (TT.getArch() == Triple::x86_64) {
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addPass(createCFGuardDispatchPass());
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} else {
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addPass(createCFGuardCheckPass());
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}
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}
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}
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bool X86PassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
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// For ELF, cleanup any local-dynamic TLS accesses.
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if (TM->getTargetTriple().isOSBinFormatELF() &&
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getOptLevel() != CodeGenOpt::None)
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addPass(createCleanupLocalDynamicTLSPass());
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addPass(createX86GlobalBaseRegPass());
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return false;
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}
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bool X86PassConfig::addIRTranslator() {
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addPass(new IRTranslator());
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return false;
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}
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bool X86PassConfig::addLegalizeMachineIR() {
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addPass(new Legalizer());
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return false;
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}
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bool X86PassConfig::addRegBankSelect() {
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addPass(new RegBankSelect());
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return false;
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}
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bool X86PassConfig::addGlobalInstructionSelect() {
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addPass(new InstructionSelect());
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return false;
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}
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bool X86PassConfig::addILPOpts() {
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if (EnableCondBrFoldingPass)
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addPass(createX86CondBrFolding());
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addPass(&EarlyIfConverterID);
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if (EnableMachineCombinerPass)
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addPass(&MachineCombinerID);
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addPass(createX86CmovConverterPass());
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return true;
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}
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bool X86PassConfig::addPreISel() {
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// Only add this pass for 32-bit x86 Windows.
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const Triple &TT = TM->getTargetTriple();
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if (TT.isOSWindows() && TT.getArch() == Triple::x86)
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addPass(createX86WinEHStatePass());
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return true;
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}
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void X86PassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(&LiveRangeShrinkID);
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addPass(createX86FixupSetCC());
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addPass(createX86OptimizeLEAs());
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addPass(createX86CallFrameOptimization());
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addPass(createX86AvoidStoreForwardingBlocks());
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}
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addPass(createX86SpeculativeLoadHardeningPass());
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addPass(createX86FlagsCopyLoweringPass());
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addPass(createX86WinAllocaExpander());
|
|
}
|
|
void X86PassConfig::addMachineSSAOptimization() {
|
|
addPass(createX86DomainReassignmentPass());
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|
TargetPassConfig::addMachineSSAOptimization();
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|
}
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|
|
|
void X86PassConfig::addPostRegAlloc() {
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|
addPass(createX86FloatingPointStackifierPass());
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|
// When -O0 is enabled, the Load Value Injection Hardening pass will fall back
|
|
// to using the Speculative Execution Side Effect Suppression pass for
|
|
// mitigation. This is to prevent slow downs due to
|
|
// analyses needed by the LVIHardening pass when compiling at -O0.
|
|
if (getOptLevel() != CodeGenOpt::None)
|
|
addPass(createX86LoadValueInjectionLoadHardeningPass());
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|
}
|
|
|
|
void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
|
|
|
|
void X86PassConfig::addPreEmitPass() {
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
|
addPass(new X86ExecutionDomainFix());
|
|
addPass(createBreakFalseDeps());
|
|
}
|
|
|
|
addPass(createX86IndirectBranchTrackingPass());
|
|
|
|
addPass(createX86IssueVZeroUpperPass());
|
|
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
|
addPass(createX86FixupBWInsts());
|
|
addPass(createX86PadShortFunctions());
|
|
addPass(createX86FixupLEAs());
|
|
}
|
|
addPass(createX86EvexToVexInsts());
|
|
addPass(createX86DiscriminateMemOpsPass());
|
|
addPass(createX86InsertPrefetchPass());
|
|
addPass(createX86InsertX87waitPass());
|
|
}
|
|
|
|
void X86PassConfig::addPreEmitPass2() {
|
|
const Triple &TT = TM->getTargetTriple();
|
|
const MCAsmInfo *MAI = TM->getMCAsmInfo();
|
|
|
|
// The X86 Speculative Execution Pass must run after all control
|
|
// flow graph modifying passes. As a result it was listed to run right before
|
|
// the X86 Retpoline Thunks pass. The reason it must run after control flow
|
|
// graph modifications is that the model of LFENCE in LLVM has to be updated
|
|
// (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
|
|
// placement of this pass was hand checked to ensure that the subsequent
|
|
// passes don't move the code around the LFENCEs in a way that will hurt the
|
|
// correctness of this pass. This placement has been shown to work based on
|
|
// hand inspection of the codegen output.
|
|
addPass(createX86SpeculativeExecutionSideEffectSuppression());
|
|
addPass(createX86IndirectThunksPass());
|
|
|
|
// Insert extra int3 instructions after trailing call instructions to avoid
|
|
// issues in the unwinder.
|
|
if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
|
|
addPass(createX86AvoidTrailingCallPass());
|
|
|
|
// Verify basic block incoming and outgoing cfa offset and register values and
|
|
// correct CFA calculation rule where needed by inserting appropriate CFI
|
|
// instructions.
|
|
if (!TT.isOSDarwin() &&
|
|
(!TT.isOSWindows() ||
|
|
MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
|
|
addPass(createCFIInstrInserter());
|
|
// Identify valid longjmp targets for Windows Control Flow Guard.
|
|
if (TT.isOSWindows())
|
|
addPass(createCFGuardLongjmpPass());
|
|
addPass(createX86LoadValueInjectionRetHardeningPass());
|
|
}
|
|
|
|
std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
|
|
return getStandardCSEConfigForOpt(TM->getOptLevel());
|
|
}
|