6c4caae449
- Move the code generated by DecoderEmitter to anonymous namespace. - Move AMDGPU's usage of this code from header file to .cpp file. Note, we get build errors like "call to function 'decodeInstruction' that is neither visible in the template definition nor found by argument-dependent lookup" if we do not change AMDGPU.
300 lines
10 KiB
C++
300 lines
10 KiB
C++
//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains declaration for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#include "SIDefines.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/DataExtractor.h"
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#include <memory>
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namespace llvm {
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class MCAsmInfo;
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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class Twine;
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// Exposes an interface expected by autogenerated code in
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// FixedLenDecoderEmitter
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class DecoderUInt128 {
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private:
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uint64_t Lo = 0;
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uint64_t Hi = 0;
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public:
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DecoderUInt128() = default;
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DecoderUInt128(uint64_t Lo, uint64_t Hi = 0) : Lo(Lo), Hi(Hi) {}
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operator bool() const { return Lo || Hi; }
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void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits) {
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assert(NumBits && NumBits <= 64);
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assert(SubBits >> 1 >> (NumBits - 1) == 0);
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assert(BitPosition < 128);
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if (BitPosition < 64) {
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Lo |= SubBits << BitPosition;
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Hi |= SubBits >> 1 >> (63 - BitPosition);
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} else {
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Hi |= SubBits << (BitPosition - 64);
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}
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}
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uint64_t extractBitsAsZExtValue(unsigned NumBits,
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unsigned BitPosition) const {
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assert(NumBits && NumBits <= 64);
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assert(BitPosition < 128);
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uint64_t Val;
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if (BitPosition < 64)
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Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
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else
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Val = Hi >> (BitPosition - 64);
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return Val & ((uint64_t(2) << (NumBits - 1)) - 1);
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}
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DecoderUInt128 operator&(const DecoderUInt128 &RHS) const {
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return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
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}
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DecoderUInt128 operator&(const uint64_t &RHS) const {
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return *this & DecoderUInt128(RHS);
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}
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DecoderUInt128 operator~() const { return DecoderUInt128(~Lo, ~Hi); }
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bool operator==(const DecoderUInt128 &RHS) {
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return Lo == RHS.Lo && Hi == RHS.Hi;
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}
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bool operator!=(const DecoderUInt128 &RHS) {
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return Lo != RHS.Lo || Hi != RHS.Hi;
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}
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bool operator!=(const int &RHS) {
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return *this != DecoderUInt128(RHS);
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}
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friend raw_ostream &operator<<(raw_ostream &OS, const DecoderUInt128 &RHS) {
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return OS << APInt(128, {RHS.Lo, RHS.Hi});
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}
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};
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//===----------------------------------------------------------------------===//
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// AMDGPUDisassembler
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//===----------------------------------------------------------------------===//
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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std::unique_ptr<MCInstrInfo const> const MCII;
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const MCRegisterInfo &MRI;
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const MCAsmInfo &MAI;
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const unsigned TargetMaxInstBytes;
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mutable ArrayRef<uint8_t> Bytes;
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mutable uint32_t Literal;
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mutable uint64_t Literal64;
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mutable bool HasLiteral;
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mutable std::optional<bool> EnableWavefrontSize32;
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unsigned CodeObjectVersion;
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const MCExpr *UCVersionW64Expr;
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const MCExpr *UCVersionW32Expr;
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const MCExpr *UCVersionMDPExpr;
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const MCExpr *createConstantSymbolExpr(StringRef Id, int64_t Val);
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII);
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~AMDGPUDisassembler() override = default;
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void setABIVersion(unsigned Version) override;
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CS) const override;
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const char* getRegClassName(unsigned RegClassID) const;
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MCOperand createRegOperand(unsigned int RegId) const;
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MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
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MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
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MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
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template <typename InsnType>
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DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
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uint64_t Address, raw_ostream &Comments) const;
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template <typename InsnType>
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DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
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MCInst &MI, InsnType Inst, uint64_t Address,
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raw_ostream &Comments) const;
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Expected<bool> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address) const override;
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Expected<bool> decodeKernelDescriptor(StringRef KdName,
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ArrayRef<uint8_t> Bytes,
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uint64_t KdAddress) const;
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Expected<bool>
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decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor,
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ArrayRef<uint8_t> Bytes,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC1.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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Expected<bool> decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC2.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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Expected<bool> decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC3.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC3.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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Expected<bool> decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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void convertEXPInst(MCInst &MI) const;
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void convertVINTERPInst(MCInst &MI) const;
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void convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
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void convertSDWAInst(MCInst &MI) const;
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void convertMAIInst(MCInst &MI) const;
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void convertDPP8Inst(MCInst &MI) const;
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void convertMIMGInst(MCInst &MI) const;
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void convertVOP3DPPInst(MCInst &MI) const;
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void convertVOP3PDPPInst(MCInst &MI) const;
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void convertVOPCDPPInst(MCInst &MI) const;
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void convertVOPC64DPPInst(MCInst &MI) const;
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void convertMacDPPInst(MCInst &MI) const;
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void convertTrue16OpSel(MCInst &MI) const;
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enum OpWidthTy {
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OPW32,
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OPW64,
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OPW96,
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OPW128,
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OPW160,
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OPW192,
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OPW256,
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OPW288,
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OPW320,
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OPW352,
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OPW384,
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OPW512,
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OPW1024,
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OPW16,
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OPWV216,
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OPWV232,
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OPW_LAST_,
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OPW_FIRST_ = OPW32
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};
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unsigned getVgprClassId(const OpWidthTy Width) const;
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unsigned getAgprClassId(const OpWidthTy Width) const;
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unsigned getSgprClassId(const OpWidthTy Width) const;
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unsigned getTtmpClassId(const OpWidthTy Width) const;
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static MCOperand decodeIntImmed(unsigned Imm);
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static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm,
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AMDGPU::OperandSemantics Sema);
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MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
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MCOperand decodeLiteralConstant(bool ExtendFP64) const;
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MCOperand decodeSrcOp(
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const OpWidthTy Width, unsigned Val, bool MandatoryLiteral = false,
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unsigned ImmWidth = 0,
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AMDGPU::OperandSemantics Sema = AMDGPU::OperandSemantics::INT) const;
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MCOperand decodeNonVGPRSrcOp(
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const OpWidthTy Width, unsigned Val, bool MandatoryLiteral = false,
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unsigned ImmWidth = 0,
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AMDGPU::OperandSemantics Sema = AMDGPU::OperandSemantics::INT) const;
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MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
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MCOperand decodeSpecialReg32(unsigned Val) const;
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MCOperand decodeSpecialReg64(unsigned Val) const;
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MCOperand decodeSpecialReg96Plus(unsigned Val) const;
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MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val,
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unsigned ImmWidth,
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AMDGPU::OperandSemantics Sema) const;
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MCOperand decodeSDWASrc16(unsigned Val) const;
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MCOperand decodeSDWASrc32(unsigned Val) const;
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MCOperand decodeSDWAVopcDst(unsigned Val) const;
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MCOperand decodeBoolReg(unsigned Val) const;
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MCOperand decodeSplitBarrier(unsigned Val) const;
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MCOperand decodeDpp8FI(unsigned Val) const;
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MCOperand decodeVersionImm(unsigned Imm) const;
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int getTTmpIdx(unsigned Val) const;
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const MCInstrInfo *getMCII() const { return MCII.get(); }
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bool isVI() const;
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bool isGFX9() const;
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bool isGFX90A() const;
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bool isGFX9Plus() const;
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bool isGFX10() const;
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bool isGFX10Plus() const;
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bool isGFX11() const;
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bool isGFX11Plus() const;
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bool isGFX12() const;
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bool isGFX12Plus() const;
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bool hasArchitectedFlatScratch() const;
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bool hasKernargPreload() const;
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bool isMacDPP(MCInst &MI) const;
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};
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//===----------------------------------------------------------------------===//
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// AMDGPUSymbolizer
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//===----------------------------------------------------------------------===//
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class AMDGPUSymbolizer : public MCSymbolizer {
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private:
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void *DisInfo;
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std::vector<uint64_t> ReferencedAddresses;
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public:
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AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
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void *disInfo)
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: MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
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bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
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int64_t Value, uint64_t Address, bool IsBranch,
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uint64_t Offset, uint64_t OpSize,
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uint64_t InstSize) override;
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void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
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int64_t Value,
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uint64_t Address) override;
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ArrayRef<uint64_t> getReferencedAddresses() const override {
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return ReferencedAddresses;
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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