llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
Brox Chen 6dbc01e801
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
This is a NFC patch.

This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script

For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.

This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.
2025-04-23 13:06:52 -04:00

151 lines
8.7 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=PREGFX10-UNPACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
define amdgpu_ps half @tbuffer_load_d16_x(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x00,0xb4,0xe8,0x00,0x00,0x00,0x80]
; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
;
; PREGFX10-PACKED-LABEL: tbuffer_load_d16_x:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; PREGFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX10-PACKED-LABEL: tbuffer_load_d16_x:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-LABEL: tbuffer_load_d16_x:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: tbuffer_load_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call half @llvm.amdgcn.raw.ptr.tbuffer.load.f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
ret half %data
}
define amdgpu_ps half @tbuffer_load_d16_xy(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xy:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xy v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x80,0xb4,0xe8,0x00,0x00,0x00,0x80]
; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v1 ; encoding: [0x01,0x03,0x00,0x7e]
; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
;
; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xy:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; PREGFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX10-PACKED-LABEL: tbuffer_load_d16_xy:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-LABEL: tbuffer_load_d16_xy:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xy v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v2f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <2 x half> %data, i32 1
ret half %elt
}
define amdgpu_ps half @tbuffer_load_d16_xyz(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyz:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyz v[0:2], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x00,0xb5,0xe8,0x00,0x00,0x00,0x80]
; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v2 ; encoding: [0x02,0x03,0x00,0x7e]
; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
;
; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
; PREGFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
; GFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED-TRUE16: ; %bb.0: ; %main_body
; GFX11-PACKED-TRUE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX11-PACKED-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
; GFX11-PACKED-FAKE16: ; %bb.0: ; %main_body
; GFX11-PACKED-FAKE16-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-FAKE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-PACKED-FAKE16-NEXT: ; return to shader part epilog
main_body:
%data = call <3 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v3f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <3 x half> %data, i32 2
ret half %elt
}
define amdgpu_ps half @tbuffer_load_d16_xyzw(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyzw:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x80,0xb5,0xe8,0x00,0x00,0x00,0x80]
; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v3 ; encoding: [0x03,0x03,0x00,0x7e]
; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
;
; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; PREGFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX10-PACKED-NEXT: ; return to shader part epilog
;
; GFX11-PACKED-LABEL: tbuffer_load_d16_xyzw:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyzw v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v4f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <4 x half> %data, i32 3
ret half %elt
}
declare half @llvm.amdgcn.raw.ptr.tbuffer.load.f16(ptr addrspace(8), i32, i32, i32, i32)
declare <2 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v2f16(ptr addrspace(8), i32, i32, i32, i32)
declare <3 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v3f16(ptr addrspace(8), i32, i32, i32, i32)
declare <4 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v4f16(ptr addrspace(8), i32, i32, i32, i32)