shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/NVPTX
History
Alex MacLean 978df3b9f1
[NVPTX][test] Fixup to get ptxas passing for byval-const-global.ll (#138175)
2025-05-01 12:38:39 -07:00
..
access-non-generic.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
activemask.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
add-sub-128bit.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
addr-mode.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
addrspacecast-cse.ll
[SDAG] Fix CSE for ADDRSPACECAST nodes (#122912)
2025-01-20 09:09:22 -08:00
addrspacecast-folding.ll
[NVPTX] Add some basic folds for ADDRSPACECAST (#129157)
2025-02-28 12:31:55 -08:00
addrspacecast-gvar.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
addrspacecast-ptx64.ll
[NVPTX] Fix ptxas tests from #135444 (#136782)
2025-04-22 16:19:28 -07:00
addrspacecast.ll
[NVPTX] Lower invalid ISD::ADDRSPACECAST (#125607)
2025-02-11 15:36:07 -08:00
aggr-param.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
aggregate-return.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
alias-errors.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
alias.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
and-or-setcc.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
annotations.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
anonymous-fn-param.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntLoadStore.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntSextParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntZextParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
applypriority.ll
[NVPTX] Add Intrinsics for applypriority.* (#127989)
2025-02-27 16:10:29 +05:30
arg-lowering.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
arithmetic-fp-sm20.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
arithmetic-int.ll
[NVPTX] Add some more immediate instruction variants (#122746)
2025-01-14 21:28:29 -08:00
async-copy.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
atomic-lower-local.ll
…
atomicrmw-expand.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
atomics-sm60.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
atomics-sm70.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
atomics-sm90.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
atomics-with-scope.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
atomics.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
b52037.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
barrier.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bf16-instructions.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
bf16.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bf16x2-instructions-approx.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
bf16x2-instructions.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
bfe.ll
[NVPTX] Fix bug in sign of bfe folding (#130862)
2025-03-12 10:19:58 -07:00
boolean-patterns.ll
[DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)
2025-02-03 16:36:01 +00:00
branch-fold.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
branch-fold.mir
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
brkpt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bswap.ll
[NVPTX] Use sink registers instead of temp registers where possible. (#134957)
2025-04-10 11:13:33 -07:00
bug17709.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bug21465.ll
[NVPTX] Improve kernel byval parameter lowering (#136008)
2025-04-21 15:55:06 -07:00
bug22246.ll
[NVPTX] Lower i1 select with logical ops in the general case (#135868)
2025-04-16 21:14:00 -07:00
bug22322.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
bug26185-2.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
bug26185.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
bug41651.ll
…
bug52623.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bypass-div.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
byval-const-global.ll
[NVPTX][test] Fixup to get ptxas passing for byval-const-global.ll (#138175)
2025-05-01 12:38:39 -07:00
call_bitcast_byval.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
call-with-alloca-buffer.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
callchain.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
calling-conv.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
calls-with-phi.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
chain-different-as.ll
[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)
2024-12-19 07:55:03 -08:00
cluster-dim.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
cmpxchg-sm60.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
cmpxchg-sm70.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
cmpxchg-sm90.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
cmpxchg.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
cmpxchg.py
[NVPTX] Support for memory orderings for cmpxchg (#126159)
2025-02-24 10:13:23 -08:00
combine-mad.ll
[NVPTX] Use 0 immediate for i1 trunc, cleanup dead code (#135646)
2025-04-14 16:50:19 -07:00
combine-min-max.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
common-linkage.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
compare-int.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
compute-ptx-value-vts.ll
[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)
2024-12-19 07:55:03 -08:00
constant-vectors.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
convergent-mir-call.ll
…
convert-call-to-indirect.ll
[NVPTX] Verify ptx in the right version
2024-09-17 10:40:21 +02:00
convert-fp-i8.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
convert-fp.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
convert-int-sm20.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
convert-sm80.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
convert-sm89.ll
[NVPTX] Add float to tf32 conversion intrinsics (#121507)
2025-01-13 16:17:42 +05:30
convert-sm90.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
convert-sm100.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
convert-sm100a.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
copysign.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
cp-async-bulk-tensor-g2s.ll
[NVPTX] Add support for Shared Cluster Memory address space [2/2] (#136768)
2025-04-22 16:50:45 -07:00
cp-async-bulk-tensor-prefetch.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
cp-async-bulk-tensor-reduce.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
cp-async-bulk-tensor-s2g.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
cp-async-bulk.ll
[NVPTX] Add support for Shared Cluster Memory address space [2/2] (#136768)
2025-04-22 16:50:45 -07:00
ctlz.ll
[NVPTX] Legalize ctpop and ctlz in operation legalization (#130668)
2025-03-12 09:28:40 -07:00
ctpop.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
cttz.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
dag-cse.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
demote-vars.ll
[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)
2024-12-19 07:55:03 -08:00
disable-opt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
discard.ll
[NVPTX] Add Intrinsics for discard.* (#128404)
2025-03-03 22:53:49 +05:30
disjoint-or-addr.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
distributed-shared-cluster.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
div-ri.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
div.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
divrem-combine.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
dot-product.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
dynamic_stackalloc.ll
[NVPTX] Remove NVPTX::IMAD opcode, and rely on intruction selection only (#121724)
2025-01-15 20:09:18 +00:00
dynamic-stackalloc-regression.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
elect.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
empty-type.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
envreg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
extloadv.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
extractelement.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
f16-abs.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
f16-ex2.ll
[NVPTX] Improve support for {ex2,lg2}.approx (#120519)
2025-01-16 12:21:32 -08:00
f16-instructions.ll
[NVPTX] Use 0 immediate for i1 trunc, cleanup dead code (#135646)
2025-04-14 16:50:19 -07:00
f16x2-instructions.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
f32-ex2.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
f32-lg2.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fabs-intrinsics.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fast-math.ll
[NVPTX] Use fast-math flags when lowering sin, cos, frem (#133121)
2025-03-28 14:13:36 -07:00
fcos-no-fast-math.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fence-cluster.ll
[NVPTX] fix ptxas tests introduced by #124865 (#125927)
2025-02-05 15:47:05 -08:00
fence-nocluster.ll
[NVPTX] fix ptxas tests introduced by #124865 (#125927)
2025-02-05 15:47:05 -08:00
fence-proxy-tensormap.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fence.py
[NVPTX] Support for fence.acquire and fence.release (#124865)
2025-02-04 14:20:00 -08:00
fexp2.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
filetype-null.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
flo.ll
[NVPTX] Add support for nvvm.flo.[us] intrinsics (#114489)
2024-11-01 16:35:43 -07:00
flog2.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fma-assoc.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fma-disable.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fma-relu-contract.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fma-relu-fma-intrinsic.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fma-relu-instruction-flag.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fma.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
fminimum-fmaximum.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fns.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
forward-ld-param.ll
[NVPTX] Improve kernel byval parameter lowering (#136008)
2025-04-21 15:55:06 -07:00
fp16.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fp128-storage-type.ll
[NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
2025-04-22 15:34:51 -07:00
fp-contract.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fp-literals.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
frem.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
fsin-no-fast-math.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
function-align.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
funnel-shift-clamp.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
generic-to-nvvm-ir.ll
…
generic-to-nvvm.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
global-addrspace.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-ctor-empty.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-incomplete-init.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-ordering.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-variable-big.ll
[NVPTX] Basic support for fp128 as a storage type (#136006)
2025-04-17 13:19:48 -07:00
global-visibility.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
globals_init.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
globals_lowering.ll
…
griddepcontrol.ll
[NVPTX] Fix ptxas failures (NFC) (#125147)
2025-02-01 16:44:37 -08:00
gvar-init.ll
[NVPTX][test] Use 'not' to switch an XFAIL test to PASS (#130839)
2025-03-12 09:20:48 -07:00
half.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i1-array-global.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-ext-load.ll
[InferAS] Support getAssumedAddrSpace for Arguments for NVPTX (#133991)
2025-04-03 16:47:36 -07:00
i1-global.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-icmp.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i1-int-to-fp.ll
[NVPTX] Use 0 immediate for i1 trunc, cleanup dead code (#135646)
2025-04-14 16:50:19 -07:00
i1-load-lower.ll
[NVPTX] Use 0 immediate for i1 trunc, cleanup dead code (#135646)
2025-04-14 16:50:19 -07:00
i1-param.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-select.ll
[NVPTX] Lower i1 select with logical ops in the general case (#135868)
2025-04-16 21:14:00 -07:00
i8-param.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i8x2-instructions.ll
[NVPTX][NFC] Regenerate some tests checks (#116605)
2024-11-18 18:35:44 +00:00
i8x4-instructions.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
i16x2-instructions.ll
[NVPTX] Use 0 immediate for i1 trunc, cleanup dead code (#135646)
2025-04-14 16:50:19 -07:00
i128-array.ll
[NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
2025-04-22 15:34:51 -07:00
i128-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i128-ld-st.ll
[NVPTX] Fixup EXT_LOAD lowering for i128 values (#138049)
2025-04-30 20:51:55 -07:00
i128-param.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i128-retval.ll
[NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
2025-04-22 15:34:51 -07:00
i128-struct.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i128.ll
[NVPTX] Lower i1 select with logical ops in the general case (#135868)
2025-04-16 21:14:00 -07:00
idioms.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
imad.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
indirect_byval.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
inline-asm-b128-test1.ll
[NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
2025-04-22 15:34:51 -07:00
inline-asm-b128-test2.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
inline-asm-b128-test3.ll
[NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
2025-04-22 15:34:51 -07:00
inline-asm.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
inlineasm-output-template.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
intr-range.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
intrinsic-old.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
intrinsics-sm90.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
intrinsics.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
isspacep.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
jump-table.ll
[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)
2024-10-19 10:05:36 -04:00
kernel-param-align.ll
[NVPTX] Fix ptxas failures (NFC) (#125147)
2025-02-01 16:44:37 -08:00
ld-addrspace.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
ld-generic.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
ld-st-addrrspace.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
ldg-invariant.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
ldparam-v4.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
ldu-i8.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
ldu-ldg.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
ldu-reg-plus-offset.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
lit.local.cfg
[NVPTX] Support for memory orderings for cmpxchg (#126159)
2025-02-24 10:13:23 -08:00
load-sext-i1.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
load-store-scalars.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
load-store-sm-70.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
load-store-sm-90.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
load-store-vectors.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
load-with-non-coherent-cache.ll
[NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
2025-04-22 15:34:51 -07:00
LoadStoreVectorizer.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
local-stack-frame.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
loop-vectorize.ll
…
lower-aggr-copies.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
lower-alloca.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
lower-args-gridconstant.ll
[NVPTX] Improve kernel byval parameter lowering (#136008)
2025-04-21 15:55:06 -07:00
lower-args.ll
[NVPTX] Improve kernel byval parameter lowering (#136008)
2025-04-21 15:55:06 -07:00
lower-byval-args.ll
[NVPTX] Improve kernel byval parameter lowering (#136008)
2025-04-21 15:55:06 -07:00
lower-ctor-dtor.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
lower-kernel-ptr-arg.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
machine-sink.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
MachineSink-call.ll
…
MachineSink-convergent.ll
…
managed.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
match.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins-sm53-ptx42.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins-sm80-ptx70-autoupgrade.ll
[NVPTX] Cleanup and document nvvm.fabs intrinsics, adding f16 support (#135644)
2025-04-17 07:37:24 -07:00
math-intrins-sm80-ptx70-instcombine.ll
…
math-intrins-sm80-ptx70.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins-sm86-ptx72-autoupgrade.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins-sm86-ptx72.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
max-align.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
maxclusterrank.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
mbarrier.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
minmax-negative.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
misaligned-vector-ldst.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
misched_func_call.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
mma-no-sink-after-laneid-check.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
module-inline-asm.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
mulhi-intrins.ll
[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)
2024-10-19 10:05:36 -04:00
mulwide.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
named-barriers.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
nanosleep.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
no-extra-parens.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
noduplicate-syncthreads.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
nofunc.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
noreturn.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
nounroll.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
nvcl-param-align.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
nvptx-aa-inline-asm.ll
[NVPTX] Improve modeling of inline PTX (#130675)
2025-03-25 13:46:16 -07:00
nvptx-aa.ll
[NVPTX] Add support for Shared Cluster Memory address space [1/2] (#135444)
2025-04-22 15:14:39 -07:00
nvvm-annotations-D120129.ll
…
nvvm-reflect-arch-O0.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
nvvm-reflect-arch.ll
[NVPTX] Fix failing test and incorrect mcpu reading in reflect
2025-01-21 13:25:04 -06:00
nvvm-reflect-module-flag.ll
…
nvvm-reflect-ocl.ll
[NVPTX] Fix failing test and incorrect mcpu reading in reflect
2025-01-21 13:25:04 -06:00
nvvm-reflect-opaque.ll
[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)
2025-01-07 14:45:03 -06:00
nvvm-reflect-options.ll
[NVPTX] Improve NVVMReflect Efficiency (#134416)
2025-04-10 18:33:37 -07:00
nvvm-reflect.ll
[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)
2025-01-07 14:45:03 -06:00
packed-aggr.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
param-add.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
param-align.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
param-load-store.ll
[NVPTX] Use 0 immediate for i1 trunc, cleanup dead code (#135646)
2025-04-14 16:50:19 -07:00
param-overalign.ll
[IR] Allow alignstack attribute on return values (#130439)
2025-03-17 14:22:08 -07:00
param-vectorize-device.ll
[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)
2024-10-19 10:05:36 -04:00
param-vectorize-kernel.ll
…
pass-name.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
pow2_mask_cmp.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
pr13291-i1-store.ll
[NVPTX] Use 0 immediate for i1 trunc, cleanup dead code (#135646)
2025-04-14 16:50:19 -07:00
pr16278.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
pr17529.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
prefetch.ll
[NVPTX] Fix and refine prefetch.* intrinsics (#126899)
2025-02-13 17:54:01 +01:00
proxy-reg-erasure-ptx.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
proxy-reg-erasure.mir
[win] NFC: Rename EHCatchret to EHCont to allow for EH Continuation targets that aren't catchret instructions (#129953)
2025-03-06 09:28:44 -08:00
rcp-opt.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
read-global-variable-constant.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
reduction-intrinsics.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
redux-sync-f32.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
redux-sync.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
refl1.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
reg-copy.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
reg-types.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
rotate_64.ll
[NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (#131371)
2025-03-18 21:05:00 -07:00
rotate-add.ll
[DAGCombiner] Attempt to fold 'add' nodes to funnel-shift or rotate (#125612)
2025-04-04 15:39:24 -07:00
rotate.ll
[NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (#131371)
2025-03-18 21:05:00 -07:00
rsqrt-opt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
rsqrt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sad-intrins.ll
[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)
2024-10-19 10:05:36 -04:00
sched1.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sched2.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
setmaxnreg-sm100a.ll
[NVPTX] Update setmaxnreg intrinsic lowering (#125846)
2025-02-06 15:23:55 +00:00
setmaxnreg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sext-in-reg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sext-params.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sext-setcc.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
shfl-p.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
shfl-sync-p.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
shfl-sync.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
shfl.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
shift-parts.ll
[NVPTX] Add some more immediate instruction variants (#122746)
2025-01-14 21:28:29 -08:00
short-ptr.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
shuffle-vec-undef-init.ll
[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)
2024-12-17 15:23:22 -08:00
simple-call.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
sm-version.ll
[NVPTX] Add SM versions for 101 and 120 (#124155)
2025-01-24 16:39:52 +05:30
speculative-execution-divergent-target.ll
…
sqrt-approx.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
st_bulk.ll
[NVPTX] Fix generic address in st.bulk intrinsic (#130740)
2025-03-12 08:50:12 +05:30
st-addrspace.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
st-generic.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
st-param-imm.ll
[NVPTX] Support BFloat Store Parameter (#137074)
2025-04-24 15:45:58 -04:00
stacksaverestore.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
store-retval.ll
…
store-undef.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
surf-read-cuda.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
surf-read.ll
Reland "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC)" (#127277)
2025-02-14 18:45:14 -08:00
surf-tex.py
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
surf-write-cuda.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
surf-write.ll
Reland "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC)" (#127277)
2025-02-14 18:45:14 -08:00
symbol-naming.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
tag-invariant-loads.ll
[NVPTX] Pull invariant load identification into IR pass (#138015)
2025-05-01 10:19:46 -07:00
TailDuplication-convergent.ll
…
tcgen05-alloc.ll
[NVPTX] Add tcgen05 alloc/dealloc intrinsics (#124961)
2025-02-04 14:31:40 +05:30
tcgen05-commit.ll
[NVPTX] Add tcgen05 wait/fence/commit intrinsics (#126091)
2025-02-07 22:10:25 +05:30
tcgen05-cp.ll
[NVPTX] Add tcgen05.cp/shift intrinsics (#127669)
2025-02-19 17:55:25 +05:30
tcgen05-fence.ll
[NVPTX] Add tcgen05 wait/fence/commit intrinsics (#126091)
2025-02-07 22:10:25 +05:30
tcgen05-ld.ll
[LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions (#126740)
2025-02-27 14:56:35 +05:30
tcgen05-shift.ll
[NVPTX] Add tcgen05.cp/shift intrinsics (#127669)
2025-02-19 17:55:25 +05:30
tcgen05-st.ll
[LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions (#126740)
2025-02-27 14:56:35 +05:30
tex-read-cuda.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
tex-read.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
texsurf-queries.ll
[NVPTX] Aggressively try to replace image handles with references (#119730)
2024-12-16 11:53:30 -08:00
tid-range.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
unaligned-param-load-store.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
unfold-masked-merge-vector-variablemask.ll
[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)
2024-12-19 07:55:03 -08:00
unreachable.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
unrecognized-sm1x.ll
[NVPTX] Require asserts in unrecognized-sm1x.ll (#126105)
2025-02-06 11:17:55 -08:00
upgrade-nvvm-annotations.ll
[NVPTX] Auto-Upgrade !"align" metadata on return values to stackalign (#131726)
2025-03-24 12:00:44 -07:00
vaargs.ll
[NVPTX] Fix vaarg store alignment (#127067)
2025-02-14 12:13:37 -05:00
variadics-backend.ll
[NVPTX] Switch to untyped float registers (#137011)
2025-04-23 15:37:38 -07:00
variadics-lowering.ll
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
2024-11-06 11:53:33 +00:00
vec8.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vec-param-load.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-args.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-call.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-compare.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
vector-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-loads.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-returns.ll
[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)
2024-12-19 07:55:03 -08:00
vector-select.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-stores.ll
[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)
2024-12-17 15:23:22 -08:00
vectorize-misaligned.ll
…
vote.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
weak-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
weak-linkage.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wgmma-sm90a-fence.ll
[NVPTX] Add intrinsics for wgmma.fence PTX instructions (#120523)
2024-12-20 15:25:06 -05:00
wmma-ptx60-sm70.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx61-sm70.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx63-sm72.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx63-sm75.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx64-sm70.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx65-sm75.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx71-sm80.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx86-sm100a.py
[LLVM][NVPTX] Add support for ldmatrix extensions introduced in PTX 8.6 (#124899)
2025-03-17 20:44:52 +05:30
wmma-ptx86-sm101a.py
[LLVM][NVPTX] Add support for ldmatrix extensions introduced in PTX 8.6 (#124899)
2025-03-17 20:44:52 +05:30
wmma-ptx86-sm120a.py
[LLVM][NVPTX] Add support for ldmatrix extensions introduced in PTX 8.6 (#124899)
2025-03-17 20:44:52 +05:30
wmma.py
[LLVM][NVPTX] Add support for ldmatrix extensions introduced in PTX 8.6 (#124899)
2025-03-17 20:44:52 +05:30
zeroext-32bit.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00