a6f24c6565
Summary: We were previously selecting all constant loads to SMRD instructions and legalizing the SMRDs with non-uniform addresses during the SIFixSGPRCopesPass. This new solution is more simple and also generates much better code, because the instruction selector is able to take advantage of all the MUBUF addressing modes that are legalization pass wasn't able to. We also no longer need to generate v_add_* instructions when we have a uniform pointer and a non-uniform offset, as this is now folded into the MUBUF instruction during instruction selection. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15425 llvm-svn: 255672
85 lines
2.4 KiB
C++
85 lines
2.4 KiB
C++
//===-- AMDGPUAnnotateUniformValues.cpp - ---------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass adds amdgpu.uniform metadata to IR values so this information
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/// can be used during instruction selection.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUIntrinsicInfo.h"
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#include "llvm/Analysis/DivergenceAnalysis.h"
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#include "llvm/IR/InstVisitor.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "amdgpu-annotate-uniform"
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using namespace llvm;
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namespace {
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class AMDGPUAnnotateUniformValues : public FunctionPass,
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public InstVisitor<AMDGPUAnnotateUniformValues> {
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DivergenceAnalysis *DA;
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public:
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static char ID;
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AMDGPUAnnotateUniformValues() :
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FunctionPass(ID) { }
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bool doInitialization(Module &M) override;
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bool runOnFunction(Function &F) override;
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const char *getPassName() const override { return "AMDGPU Annotate Uniform Values"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<DivergenceAnalysis>();
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AU.setPreservesAll();
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}
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void visitLoadInst(LoadInst &I);
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};
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} // End anonymous namespace
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INITIALIZE_PASS_BEGIN(AMDGPUAnnotateUniformValues, DEBUG_TYPE,
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"Add AMDGPU uniform metadata", false, false)
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INITIALIZE_PASS_DEPENDENCY(DivergenceAnalysis)
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INITIALIZE_PASS_END(AMDGPUAnnotateUniformValues, DEBUG_TYPE,
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"Add AMDGPU uniform metadata", false, false)
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char AMDGPUAnnotateUniformValues::ID = 0;
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void AMDGPUAnnotateUniformValues::visitLoadInst(LoadInst &I) {
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Value *Ptr = I.getPointerOperand();
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if (!DA->isUniform(Ptr))
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return;
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if (Instruction *PtrI = dyn_cast<Instruction>(Ptr))
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PtrI->setMetadata("amdgpu.uniform", MDNode::get(I.getContext(), {}));
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}
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bool AMDGPUAnnotateUniformValues::doInitialization(Module &M) {
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return false;
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}
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bool AMDGPUAnnotateUniformValues::runOnFunction(Function &F) {
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DA = &getAnalysis<DivergenceAnalysis>();
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visit(F);
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return true;
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}
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FunctionPass *
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llvm::createAMDGPUAnnotateUniformValues() {
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return new AMDGPUAnnotateUniformValues();
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}
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