e0bd8d3485
When only an exclusive target e.g AArch64 was enabled, these tests were previously shown as UNSUPPORTED. This change allows us to run tests for cases with only a build for one target.
78 lines
4.2 KiB
LLVM
78 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: %if x86-registered-target %{ opt -passes=slp-vectorizer -S -mtriple=x86_64 < %s | FileCheck %s %}
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; RUN: %if aarch64-registered-target %{ opt -passes=slp-vectorizer -S -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}
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define double @test() {
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; CHECK-LABEL: define double @test() {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr null, align 8
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; CHECK-NEXT: br label [[COND_TRUE:%.*]]
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; CHECK: cond.true:
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
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; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP3]], zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x double> [[TMP6]], zeroinitializer
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; CHECK-NEXT: [[TMP8:%.*]] = fsub <2 x double> [[TMP7]], zeroinitializer
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; CHECK-NEXT: [[TMP9:%.*]] = fmul <2 x double> [[TMP7]], zeroinitializer
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; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP8]], <2 x double> [[TMP9]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: [[TMP11:%.*]] = fadd <2 x double> zeroinitializer, [[TMP10]]
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; CHECK-NEXT: [[TMP12:%.*]] = fmul <2 x double> zeroinitializer, [[TMP10]]
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; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x double> [[TMP11]], <2 x double> [[TMP12]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: [[TMP14:%.*]] = fsub <2 x double> [[TMP13]], [[TMP2]]
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; CHECK-NEXT: [[TMP15:%.*]] = fadd <2 x double> [[TMP13]], [[TMP2]]
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; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x double> [[TMP14]], <2 x double> [[TMP15]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: [[TMP17:%.*]] = fsub <2 x double> [[TMP16]], zeroinitializer
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; CHECK-NEXT: [[TMP18:%.*]] = fmul <2 x double> [[TMP4]], zeroinitializer
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; CHECK-NEXT: [[TMP19:%.*]] = fmul <2 x double> zeroinitializer, [[TMP18]]
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; CHECK-NEXT: [[TMP20:%.*]] = fadd <2 x double> [[TMP19]], [[TMP17]]
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; CHECK-NEXT: [[TMP21:%.*]] = fsub <2 x double> [[TMP20]], zeroinitializer
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; CHECK-NEXT: [[TMP22:%.*]] = fmul <2 x double> [[TMP5]], zeroinitializer
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; CHECK-NEXT: [[TMP23:%.*]] = fmul <2 x double> zeroinitializer, [[TMP22]]
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; CHECK-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[TMP23]], [[TMP21]]
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; CHECK-NEXT: [[TMP25:%.*]] = extractelement <2 x double> [[TMP24]], i32 0
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; CHECK-NEXT: [[TMP26:%.*]] = extractelement <2 x double> [[TMP24]], i32 1
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; CHECK-NEXT: [[ADD29:%.*]] = fadd double [[TMP25]], [[TMP26]]
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; CHECK-NEXT: ret double [[ADD29]]
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;
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entry:
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%0 = load double, ptr null, align 8
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br label %cond.true
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cond.true:
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%mul13 = fmul double %0, 0.000000e+00
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%mul14 = fmul double %0, 0.000000e+00
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%mul15 = fmul double %mul14, 0.000000e+00
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%mul16 = fmul double 0.000000e+00, %mul15
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%add17 = fadd double %mul13, %mul16
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%sub18 = fsub double %add17, 0.000000e+00
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%mul19 = fmul double %0, 0.000000e+00
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%mul20 = fmul double %mul19, 0.000000e+00
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%mul21 = fmul double %mul20, 0.000000e+00
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%add22 = fadd double %sub18, %mul21
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%sub23 = fsub double %add22, 0.000000e+00
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%mul24 = fmul double %0, 0.000000e+00
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%mul25 = fmul double %mul24, 0.000000e+00
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%mul26 = fmul double 0.000000e+00, %mul25
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%add27 = fadd double %mul26, %sub23
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%mul = fmul double 0.000000e+00, 0.000000e+00
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%mul1 = fmul double %mul, 0.000000e+00
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%sub = fsub double %mul1, 0.000000e+00
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%add = fadd double 0.000000e+00, %sub
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%sub2 = fsub double %add, %mul
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%sub3 = fsub double %sub2, 0.000000e+00
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%mul4 = fmul double %0, 0.000000e+00
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%mul5 = fmul double %mul4, 0.000000e+00
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%mul6 = fmul double 0.000000e+00, %mul5
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%add7 = fadd double %mul6, %sub3
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%sub8 = fsub double %add7, 0.000000e+00
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%mul9 = fmul double %0, 0.000000e+00
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%mul10 = fmul double %mul9, 0.000000e+00
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%mul11 = fmul double 0.000000e+00, %mul10
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%add12 = fadd double %mul11, %sub8
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%add29 = fadd double %add12, %add27
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ret double %add29
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}
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