9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
57 lines
2.1 KiB
LLVM
57 lines
2.1 KiB
LLVM
; RUN: llc -O0 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_branch:
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; GCNNOOPT: v_writelane_b32
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; GCNNOOPT: v_writelane_b32
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; GCN: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
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; GCNNOOPT: v_readlane_b32
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; GCNNOOPT: v_readlane_b32
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; GCN: buffer_store_{{dword|b32}}
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; GCNNOOPT: s_endpgm
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @test_branch(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %val) #0 {
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%cmp = icmp ne i32 %val, 0
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br i1 %cmp, label %store, label %end
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store:
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store i32 222, ptr addrspace(1) %out
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ret void
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end:
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ret void
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}
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; GCN-LABEL: {{^}}test_brcc_i1:
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; GCN: s_load_{{dword|b32}} [[VAL:s[0-9]+]]
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; GCNNOOPT: s_mov_b32 [[ONE:s[0-9]+]], 1{{$}}
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; GCNNOOPT: s_and_b32 s{{[0-9]+}}, [[VAL]], [[ONE]]
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; GCNOPT: s_bitcmp0_b32 [[VAL]], 0
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; GCNNOOPT: s_cmp_eq_u32
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; GCN: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
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; GCN: buffer_store_{{dword|b32}}
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @test_brcc_i1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i1 %val) #0 {
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%cmp0 = icmp ne i1 %val, 0
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br i1 %cmp0, label %store, label %end
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store:
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store i32 222, ptr addrspace(1) %out
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ret void
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end:
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ret void
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}
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attributes #0 = { nounwind }
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