dc84770d55
This is a first attempt at a constant value consecutive store merging pass, a counterpart to the DAGCombiner's store merging optimization. The high level goals of this pass: * Have a simple and efficient algorithm. As close to linear time as we can get. Thus, prioritizing scalability of the algorithm over merging every corner case we can find. The DAGCombiner's store merging code has been the source of compile time and complexity issues in the past and I wanted to avoid that. * Don't introduce any new data structures for ordering memory operations. In MIR, we don't have the concept of chains like we do in the DAG, and the instruction order is stricter than enforcing ordering with graph edges. Although I considered adding something similar, I couldn't justify the overhead. The pass is current split into 3 main parts. The main store merging code focuses on identifying candidate stores and managing the candidate group that's under consideration for merging. Analyzing addressing of stores is a potentially complex part and for now there's just a basic implementation to identify easy cases. Finally, the other main bit of complexity is the alias analysis, which tries to follow the same logic as the DAG's AA. Currently this implementation only supports merging of constant stores. Stores of arbitrary variables are technically possible with a very small change, but the DAG chooses not to do this. Doing so here makes most code worse since there's extra overhead in merging values into wider registers. On AArch64 -Os, this optimization results in very minor savings on CTMark. Differential Revision: https://reviews.llvm.org/D109131
93 lines
4.0 KiB
LLVM
93 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -O0 \
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; RUN: | FileCheck %s --check-prefixes=ENABLED,FALLBACK
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs -O0 \
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; RUN: | FileCheck %s --check-prefixes=ENABLED,FALLBACK,VERIFY,VERIFY-O0
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -O0 -aarch64-enable-global-isel-at-O=0 -global-isel-abort=1 \
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; RUN: | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -O0 -aarch64-enable-global-isel-at-O=0 -global-isel-abort=2 \
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; RUN: | FileCheck %s --check-prefixes=ENABLED,FALLBACK
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -global-isel \
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; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK --check-prefix ENABLED-O1
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -global-isel -global-isel-abort=2 \
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; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix FALLBACK --check-prefix ENABLED-O1
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=3 \
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; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O1
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=0 \
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; RUN: | FileCheck %s --check-prefix DISABLED
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 -aarch64-enable-global-isel-at-O=-1 \
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; RUN: | FileCheck %s --check-prefix DISABLED
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -verify-machineinstrs=0 | FileCheck %s --check-prefix DISABLED
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; RUN: llc -mtriple=aarch64-- -fast-isel=0 -global-isel=false \
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; RUN: --debugify-and-strip-all-safe=0 \
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; RUN: -debug-pass=Structure %s -o /dev/null 2>&1 -verify-machineinstrs=0 \
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; RUN: | FileCheck %s --check-prefix DISABLED
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; ENABLED: IRTranslator
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED-NEXT: Analysis for ComputingKnownBits
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; ENABLED-O1-NEXT: MachineDominator Tree Construction
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; ENABLED-O1-NEXT: Analysis containing CSE Info
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; ENABLED-O1-NEXT: PreLegalizerCombiner
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; VERIFY-O0-NEXT: AArch64O0PreLegalizerCombiner
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED-O1-NEXT: Basic Alias Analysis (stateless AA impl)
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; ENABLED-O1-NEXT: Function Alias Analysis Results
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; ENABLED-O1-NEXT: LoadStoreOpt
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; ENABLED-O1-NEXT: Analysis containing CSE Info
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; VERIFY-O0-NEXT: Analysis containing CSE Info
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; ENABLED-NEXT: Legalizer
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED: RegBankSelect
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED-NEXT: Localizer
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; VERIFY-O0-NEXT: Verify generated machine code
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; ENABLED-O1-NEXT: Analysis for ComputingKnownBits
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; ENABLED-O1-NEXT: Lazy Branch Probability Analysis
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; ENABLED-O1-NEXT: Lazy Block Frequency Analysis
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; ENABLED-NEXT: InstructionSelect
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; ENABLED-O1-NEXT: AArch64 Post Select Optimizer
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED-NEXT: ResetMachineFunction
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; FALLBACK: AArch64 Instruction Selection
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; NOFALLBACK-NOT: AArch64 Instruction Selection
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; DISABLED-NOT: IRTranslator
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; DISABLED: AArch64 Instruction Selection
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; DISABLED: Finalize ISel and expand pseudo-instructions
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define void @empty() {
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ret void
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}
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