adec922361
We would like to start pushing -mcpu=generic towards enabling the set of features that improves performance for some CPUs, without hurting any others. A blend of the performance options hopefully beneficial to all CPUs. The largest part of that is enabling in-order scheduling using the Cortex-A55 schedule model. This is similar to the Arm backend change from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling using the cortex-a8 schedule model. The idea is that in-order cpu's require the most help in instruction scheduling, whereas out-of-order cpus can for the most part out-of-order schedule around different codegen. Our benchmarking suggests that hypothesis holds. When running on an in-order core this improved performance by 3.8% geomean on a set of DSP workloads, 2% geomean on some other embedded benchmark and between 1% and 1.8% on a set of singlecore and multicore workloads, all running on a Cortex-A55 cluster. On an out-of-order cpu the results are a lot more noisy but show flat performance or an improvement. On the set of DSP and embedded benchmarks, run on a Cortex-A78 there was a very noisy 1% speed improvement. Using the most detailed results I could find, SPEC2006 runs on a Neoverse N1 show a small increase in instruction count (+0.127%), but a decrease in cycle counts (-0.155%, on average). The instruction count is very low noise, the cycle count is more noisy with a 0.15% decrease not being significant. SPEC2k17 shows a small decrease (-0.2%) in instruction count leading to a -0.296% decrease in cycle count. These results are within noise margins but tend to show a small improvement in general. When specifying an Apple target, clang will set "-target-cpu apple-a7" on the command line, so should not be affected by this change when running from clang. This also doesn't enable more runtime unrolling like -mcpu=cortex-a55 does, only changing the schedule used. A lot of existing tests have updated. This is a summary of the important differences: - Most changes are the same instructions in a different order. - Sometimes this leads to very minor inefficiencies, such as requiring an extra mov to move variables into r0/v0 for the return value of a test function. - misched-fusion.ll was no longer fusing the pairs of instructions it should, as per D110561. I've changed the schedule used in the test for now. - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to the different latencies. This seems fine to me. - Some SVE tests do not always remove movprfx where they did before due to different register allocation giving different destructive forms. - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll produce two LDR where they previously produced an LDP due to store-pair-suppress kicking in. - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD. - Some tests such as arm64-neon-mul-div.ll and ragreedy-local-interval-cost.ll have more, less or just different spilling. - In aarch64_generated_funcs.ll.generated.expected one part of the function is no longer outlined. Interestingly if I switch this to use any other scheduled even less is outlined. Some of these are expected to happen, such as differences in outlining or register spilling. There will be places where these result in worse codegen, places where they are better, with the SPEC instruction counts suggesting it is not a decrease overall, on average. Differential Revision: https://reviews.llvm.org/D110830
172 lines
4.9 KiB
LLVM
172 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
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define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: t1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t1 = icmp sgt <4 x i32> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %t2
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}
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define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: t2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t1 = icmp slt <4 x i32> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %t2
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}
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define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: t3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t1 = icmp ugt <4 x i32> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %t2
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}
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define <8 x i8> @t4(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: t4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umin v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%t1 = icmp ult <8 x i8> %a, %b
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%t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
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ret <8 x i8> %t2
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}
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define <4 x i16> @t5(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: t5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smin v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: ret
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%t1 = icmp sgt <4 x i16> %b, %a
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%t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
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ret <4 x i16> %t2
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}
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define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: t6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smax v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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%t1 = icmp slt <2 x i32> %b, %a
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%t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
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ret <2 x i32> %t2
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}
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define <16 x i8> @t7(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: t7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umin v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%t1 = icmp ugt <16 x i8> %b, %a
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%t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %t2
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}
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define <8 x i16> @t8(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: t8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umax v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%t1 = icmp ult <8 x i16> %b, %a
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%t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %t2
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}
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define <4 x i32> @t9(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: t9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umin v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: ret
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%t1 = icmp ugt <4 x i32> %b, %a
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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%t3 = icmp sge <4 x i32> %t2, %c
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%t4 = select <4 x i1> %t3, <4 x i32> %t2, <4 x i32> %c
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ret <4 x i32> %t4
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}
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define <8 x i32> @t10(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-LABEL: t10:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: smax v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: ret
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%t1 = icmp sgt <8 x i32> %a, %b
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%t2 = select <8 x i1> %t1, <8 x i32> %a, <8 x i32> %b
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ret <8 x i32> %t2
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}
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define <16 x i32> @t11(<16 x i32> %a, <16 x i32> %b) {
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; CHECK-LABEL: t11:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smin v2.4s, v2.4s, v6.4s
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; CHECK-NEXT: smin v0.4s, v0.4s, v4.4s
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; CHECK-NEXT: smin v1.4s, v1.4s, v5.4s
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; CHECK-NEXT: smin v3.4s, v3.4s, v7.4s
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; CHECK-NEXT: ret
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%t1 = icmp sle <16 x i32> %a, %b
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%t2 = select <16 x i1> %t1, <16 x i32> %a, <16 x i32> %b
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ret <16 x i32> %t2
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}
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; The icmp is used by two instructions, so don't produce a umin node.
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define <16 x i8> @t12(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: t12:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.16b, #1
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; CHECK-NEXT: cmhi v3.16b, v1.16b, v0.16b
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; CHECK-NEXT: bif v0.16b, v1.16b, v3.16b
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; CHECK-NEXT: and v1.16b, v3.16b, v2.16b
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; CHECK-NEXT: add v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%t1 = icmp ugt <16 x i8> %b, %a
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%t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
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%t3 = zext <16 x i1> %t1 to <16 x i8>
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%t4 = add <16 x i8> %t3, %t2
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ret <16 x i8> %t4
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}
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define <1 x i64> @t13(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: t13:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmhi d2, d1, d0
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; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%t1 = icmp ult <1 x i64> %a, %b
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%t2 = select <1 x i1> %t1, <1 x i64> %a, <1 x i64> %b
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ret <1 x i64> %t2
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}
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define <2 x i64> @t14(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: t14:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmhi v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%t1 = icmp ugt <2 x i64> %a, %b
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%t2 = select <2 x i1> %t1, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %t2
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}
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define <4 x i64> @t15(<4 x i64> %a, <4 x i64> %b) {
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; CHECK-LABEL: t15:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmhi v4.2d, v2.2d, v0.2d
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; CHECK-NEXT: cmhi v5.2d, v3.2d, v1.2d
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; CHECK-NEXT: bif v0.16b, v2.16b, v4.16b
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; CHECK-NEXT: bif v1.16b, v3.16b, v5.16b
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; CHECK-NEXT: ret
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%t1 = icmp ule <4 x i64> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i64> %a, <4 x i64> %b
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ret <4 x i64> %t2
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}
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