77eafb8430
wmma intrinsics have a large number of combinations, ideally we want to be able to target all the different variants. To avoid a combinatorial explosion in the number of mlir op we use attributes to represent the different variation of load/store/mma ops. We also can generate with tablegen helpers to know which combinations are available. Using this we can avoid having too hardcode a path for specific shapes and can support more types. This patch also adds boiler plates for tf32 op support. Differential Revision: https://reviews.llvm.org/D112689
263 lines
11 KiB
C++
263 lines
11 KiB
C++
//===- NVVMDialect.cpp - NVVM IR Ops and Dialect registration -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the types and operation details for the NVVM IR dialect in
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// MLIR, and the LLVM IR dialect. It also registers the dialect.
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//
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// The NVVM dialect only contains GPU specific additions on top of the general
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// LLVM dialect.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/MLIRContext.h"
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#include "mlir/IR/Operation.h"
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#include "mlir/IR/OperationSupport.h"
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#include "llvm/AsmParser/Parser.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/SourceMgr.h"
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using namespace mlir;
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using namespace NVVM;
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#include "mlir/Dialect/LLVMIR/NVVMOpsDialect.cpp.inc"
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#include "mlir/Dialect/LLVMIR/NVVMOpsEnums.cpp.inc"
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//===----------------------------------------------------------------------===//
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// Printing/parsing for NVVM ops
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//===----------------------------------------------------------------------===//
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static void printNVVMIntrinsicOp(OpAsmPrinter &p, Operation *op) {
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p << " " << op->getOperands();
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if (op->getNumResults() > 0)
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p << " : " << op->getResultTypes();
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}
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// <operation> ::=
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// `llvm.nvvm.shfl.sync.bfly %dst, %val, %offset, %clamp_and_mask`
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// ({return_value_and_is_valid})? : result_type
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static ParseResult parseNVVMShflSyncBflyOp(OpAsmParser &parser,
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OperationState &result) {
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SmallVector<OpAsmParser::OperandType, 8> ops;
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Type resultType;
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if (parser.parseOperandList(ops) ||
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parser.parseOptionalAttrDict(result.attributes) ||
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parser.parseColonType(resultType) ||
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parser.addTypeToList(resultType, result.types))
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return failure();
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for (auto &attr : result.attributes) {
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if (attr.first != "return_value_and_is_valid")
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continue;
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auto structType = resultType.dyn_cast<LLVM::LLVMStructType>();
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if (structType && !structType.getBody().empty())
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resultType = structType.getBody()[0];
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break;
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}
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auto int32Ty = IntegerType::get(parser.getContext(), 32);
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return parser.resolveOperands(ops, {int32Ty, resultType, int32Ty, int32Ty},
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parser.getNameLoc(), result.operands);
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}
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// <operation> ::= `llvm.nvvm.vote.ballot.sync %mask, %pred` : result_type
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static ParseResult parseNVVMVoteBallotOp(OpAsmParser &parser,
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OperationState &result) {
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MLIRContext *context = parser.getContext();
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auto int32Ty = IntegerType::get(context, 32);
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auto int1Ty = IntegerType::get(context, 1);
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SmallVector<OpAsmParser::OperandType, 8> ops;
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Type type;
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return failure(parser.parseOperandList(ops) ||
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parser.parseOptionalAttrDict(result.attributes) ||
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parser.parseColonType(type) ||
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parser.addTypeToList(type, result.types) ||
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parser.resolveOperands(ops, {int32Ty, int1Ty},
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parser.getNameLoc(), result.operands));
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}
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static LogicalResult verify(MmaOp op) {
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MLIRContext *context = op.getContext();
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auto f16Ty = Float16Type::get(context);
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auto f16x2Ty = LLVM::getFixedVectorType(f16Ty, 2);
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auto f32Ty = Float32Type::get(context);
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auto f16x2x4StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty});
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auto f32x8StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty});
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SmallVector<Type, 12> operandTypes(op.getOperandTypes().begin(),
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op.getOperandTypes().end());
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if (operandTypes != SmallVector<Type, 8>(8, f16x2Ty) &&
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operandTypes != SmallVector<Type, 12>{f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty,
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f32Ty, f32Ty, f32Ty, f32Ty, f32Ty,
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f32Ty, f32Ty, f32Ty}) {
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return op.emitOpError(
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"expected operands to be 4 <halfx2>s followed by either "
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"4 <halfx2>s or 8 floats");
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}
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if (op.getType() != f32x8StructTy && op.getType() != f16x2x4StructTy) {
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return op.emitOpError("expected result type to be a struct of either 4 "
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"<halfx2>s or 8 floats");
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}
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auto alayout = op->getAttrOfType<StringAttr>("alayout");
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auto blayout = op->getAttrOfType<StringAttr>("blayout");
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if (!(alayout && blayout) ||
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!(alayout.getValue() == "row" || alayout.getValue() == "col") ||
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!(blayout.getValue() == "row" || blayout.getValue() == "col")) {
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return op.emitOpError(
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"alayout and blayout attributes must be set to either "
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"\"row\" or \"col\"");
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}
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if (operandTypes == SmallVector<Type, 12>{f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty,
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f32Ty, f32Ty, f32Ty, f32Ty, f32Ty,
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f32Ty, f32Ty, f32Ty} &&
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op.getType() == f32x8StructTy && alayout.getValue() == "row" &&
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blayout.getValue() == "col") {
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return success();
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}
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return op.emitOpError("unimplemented mma.sync variant");
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}
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std::pair<mlir::Type, unsigned>
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inferMMAType(NVVM::MMATypes type, NVVM::MMAFrag frag, MLIRContext *context) {
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unsigned numberElements = 0;
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Type elementType;
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OpBuilder builder(context);
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Type f16x2 = VectorType::get(2, builder.getF16Type());
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if (type == NVVM::MMATypes::f16) {
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elementType = f16x2;
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if (frag == NVVM::MMAFrag::a || frag == NVVM::MMAFrag::b)
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numberElements = 8;
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else
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numberElements = 4;
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} else if (type == NVVM::MMATypes::f32) {
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elementType = builder.getF32Type();
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numberElements = 8;
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} else if (type == NVVM::MMATypes::tf32) {
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elementType = builder.getI32Type();
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numberElements = 4;
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}
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assert(numberElements != 0 && elementType != nullptr);
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return std::make_pair(elementType, numberElements);
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}
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static LogicalResult verify(NVVM::WMMALoadOp op) {
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unsigned addressSpace =
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op.ptr().getType().cast<LLVM::LLVMPointerType>().getAddressSpace();
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if (addressSpace != 0 && addressSpace != 1 && addressSpace != 3)
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return op.emitOpError("expected source pointer in memory "
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"space 0, 1, 3");
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if (NVVM::WMMALoadOp::getIntrinsicID(op.m(), op.n(), op.k(), op.layout(),
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op.eltype(), op.frag()) == 0)
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return op.emitOpError() << "invalid attribute combination";
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std::pair<Type, unsigned> typeInfo =
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inferMMAType(op.eltype(), op.frag(), op.getContext());
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Type dstType = LLVM::LLVMStructType::getLiteral(
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op.getContext(), SmallVector<Type, 8>(typeInfo.second, typeInfo.first));
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if (op.getType() != dstType)
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return op.emitOpError("expected destination type is a structure of ")
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<< typeInfo.second << " elements of type " << typeInfo.first;
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return success();
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}
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static LogicalResult verify(NVVM::WMMAStoreOp op) {
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unsigned addressSpace =
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op.ptr().getType().cast<LLVM::LLVMPointerType>().getAddressSpace();
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if (addressSpace != 0 && addressSpace != 1 && addressSpace != 3)
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return op.emitOpError("expected operands to be a source pointer in memory "
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"space 0, 1, 3");
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if (NVVM::WMMAStoreOp::getIntrinsicID(op.m(), op.n(), op.k(), op.layout(),
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op.eltype()) == 0)
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return op.emitOpError() << "invalid attribute combination";
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std::pair<Type, unsigned> typeInfo =
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inferMMAType(op.eltype(), NVVM::MMAFrag::c, op.getContext());
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if (op.args().size() != typeInfo.second)
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return op.emitOpError()
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<< "expected " << typeInfo.second << " data operands";
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if (llvm::any_of(op.args(), [&typeInfo](Value operands) {
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return operands.getType() != typeInfo.first;
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}))
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return op.emitOpError()
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<< "expected data operands of type " << typeInfo.first;
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return success();
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}
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static LogicalResult verify(NVVM::WMMAMmaOp op) {
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if (NVVM::WMMAMmaOp::getIntrinsicID(op.m(), op.n(), op.k(), op.layoutA(),
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op.layoutB(), op.eltypeA(),
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op.eltypeB()) == 0)
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return op.emitOpError() << "invalid attribute combination";
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std::pair<Type, unsigned> typeInfoA =
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inferMMAType(op.eltypeA(), NVVM::MMAFrag::a, op.getContext());
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std::pair<Type, unsigned> typeInfoB =
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inferMMAType(op.eltypeA(), NVVM::MMAFrag::b, op.getContext());
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std::pair<Type, unsigned> typeInfoC =
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inferMMAType(op.eltypeB(), NVVM::MMAFrag::c, op.getContext());
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SmallVector<Type, 32> arguments;
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arguments.append(typeInfoA.second, typeInfoA.first);
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arguments.append(typeInfoB.second, typeInfoB.first);
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arguments.append(typeInfoC.second, typeInfoC.first);
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unsigned numArgs = arguments.size();
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if (op.args().size() != numArgs)
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return op.emitOpError() << "expected " << numArgs << " arguments";
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for (unsigned i = 0; i < numArgs; i++) {
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if (op.args()[i].getType() != arguments[i])
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return op.emitOpError()
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<< "expected argument " << i << " to be of type " << arguments[i];
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}
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Type dstType = LLVM::LLVMStructType::getLiteral(
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op.getContext(), SmallVector<Type, 8>(typeInfoC.second, typeInfoC.first));
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if (op.getType() != dstType)
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return op.emitOpError("expected destination type is a structure of ")
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<< typeInfoC.second << " elements of type " << typeInfoC.first;
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return success();
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}
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//===----------------------------------------------------------------------===//
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// NVVMDialect initialization, type parsing, and registration.
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//===----------------------------------------------------------------------===//
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// TODO: This should be the llvm.nvvm dialect once this is supported.
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void NVVMDialect::initialize() {
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addOperations<
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#define GET_OP_LIST
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#include "mlir/Dialect/LLVMIR/NVVMOps.cpp.inc"
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>();
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// Support unknown operations because not all NVVM operations are
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// registered.
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allowUnknownOperations();
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}
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LogicalResult NVVMDialect::verifyOperationAttribute(Operation *op,
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NamedAttribute attr) {
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// Kernel function attribute should be attached to functions.
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if (attr.first == NVVMDialect::getKernelFuncAttrName()) {
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if (!isa<LLVM::LLVMFuncOp>(op)) {
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return op->emitError() << "'" << NVVMDialect::getKernelFuncAttrName()
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<< "' attribute attached to unexpected op";
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}
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}
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return success();
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}
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#define GET_OP_CLASSES
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#include "mlir/Dialect/LLVMIR/NVVMOps.cpp.inc"
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