e1818af8c5
Changes: - Added disassembler project - Fixed all decoding conflicts in .td files - Added DecoderMethod=“NONE” option to Target.td that allows to disable decoder generation for an instruction. - Created decoding functions for VS_32 and VReg_32 register classes. - Added stubs for decoding all register classes. - Added several tests for disassembler Disassembler only supports: - VI subtarget - VOP1 instruction encoding - 32-bit register operands and inline constants [Valery] One of the point that requires to pay attention to is how decoder conflicts were resolved: - Groups of target instructions were separated by using different DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate approach. - There were conflicts in IMAGE_<> instructions caused by two different reasons: 1. dmask wasn’t specified for the output (fixed) 2. There are image instructions that differ only by the number of the address components but have the same encoding by the HW spec. The actual number of address components is determined by the HW at runtime using image resource descriptor starting from the VGPR encoded in an IMAGE instruction. This means that we should choose only one instruction from conflicting group to be the rule for decoder. I didn’t find the way to disable decoder generation for an arbitrary instruction and therefore made a onelinear fix to tablegen generator that would suppress decoder generation when DecoderMethod is set to “NONE”. This is a change that should be reviewed and submitted first. Otherwise I would need to specify different DecoderNamespace for every instruction in the conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not used in other targets. 3. IMAGE_GATHER decoder generation is for now disabled and to be done later. [/Valery] Patch By: Sam Kolton Differential Revision: http://reviews.llvm.org/D16723 llvm-svn: 261185
58 lines
2.0 KiB
C++
58 lines
2.0 KiB
C++
//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains declaration for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCSubtargetInfo;
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class AMDGPUDisassembler : public MCDisassembler {
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
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MCDisassembler(STI, Ctx) {}
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~AMDGPUDisassembler() {}
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &WS, raw_ostream &CS) const override;
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/// Decode inline float value in VSrc field
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DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
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/// Decode inline integer value in VSrc field
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DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
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/// Decode VGPR register
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DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
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/// Decode SGPR register
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DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
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/// Decode register in VSrc field
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DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;
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DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr) const;
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DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr) const;
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};
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} // namespace llvm
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#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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