2b65ed306d
Summary: These register has different encodings on CI and VI, so we add pseudo FLAT_SCRACTH registers to be used before MC, and subtarget specific registers to be used by the MC layer. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15661 llvm-svn: 256178
61 lines
1.6 KiB
C++
61 lines
1.6 KiB
C++
//===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#include "AMDKernelCodeT.h"
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namespace llvm {
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class FeatureBitset;
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class Function;
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class GlobalValue;
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class MCContext;
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class MCSection;
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class MCSubtargetInfo;
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namespace AMDGPU {
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struct IsaVersion {
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unsigned Major;
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unsigned Minor;
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unsigned Stepping;
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};
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IsaVersion getIsaVersion(const FeatureBitset &Features);
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features);
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MCSection *getHSATextSection(MCContext &Ctx);
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MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
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MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
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MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
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bool isGroupSegment(const GlobalValue *GV);
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bool isGlobalSegment(const GlobalValue *GV);
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bool isReadOnlySegment(const GlobalValue *GV);
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unsigned getShaderType(const Function &F);
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bool isSI(const MCSubtargetInfo &STI);
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bool isCI(const MCSubtargetInfo &STI);
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bool isVI(const MCSubtargetInfo &STI);
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/// If \p Reg is a pseudo reg, return the correct hardware register given
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/// \p STI otherwise return \p Reg.
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unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif
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