
The `-target` impacts the CC for the builtins. HF targets (with either floating point ABI) always use AAPCS VFP for the builtins unless they are AEABI builtins, in which case they use AAPCS. Non-HF targets (with either floating point ABI) always use AAPCS for the builtins and AAPCS for the AEABI builtins. This introduces the thunks necessary to switch CC for the floating point operations. This is not currently enabled, and should be dependent on the target being used to build compiler-rt. However, as a stop-gap, a define can be added for ASFLAGS to get the thunks. llvm-svn: 291677
35 lines
1022 B
ArmAsm
35 lines
1022 B
ArmAsm
//===-- floatunssidfvfp.S - Implement floatunssidfvfp ---------------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is dual licensed under the MIT and the University of Illinois Open
|
|
// Source Licenses. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "../assembly.h"
|
|
|
|
//
|
|
// extern double __floatunssidfvfp(unsigned int a);
|
|
//
|
|
// Converts a 32-bit int to a double precision float.
|
|
// Uses Darwin calling convention where a double precision result is
|
|
// return in GPR register pair.
|
|
//
|
|
.syntax unified
|
|
.p2align 2
|
|
DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp)
|
|
#if defined(COMPILER_RT_ARMHF_TARGET)
|
|
vmov s0, r0
|
|
vcvt.f64.u32 d0, s0
|
|
#else
|
|
vmov s15, r0 // move int to float register s15
|
|
vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
|
|
vmov r0, r1, d7 // move d7 to result register pair r0/r1
|
|
#endif
|
|
bx lr
|
|
END_COMPILERRT_FUNCTION(__floatunssidfvfp)
|
|
|
|
NO_EXEC_STACK_DIRECTIVE
|
|
|