fb94354d2d
Summary: And implement memory instructions on X86. This fixes PR36906. Reviewers: gchatelet Reviewed By: gchatelet Subscribers: lebedev.ri, filcab, mgorny, tschuett, RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D48935 llvm-svn: 338567
51 lines
1.4 KiB
C++
51 lines
1.4 KiB
C++
//===-- AssemblerTest.cpp ---------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "../Common/AssemblerUtils.h"
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#include "ARMInstrInfo.h"
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namespace exegesis {
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namespace {
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using llvm::MCInstBuilder;
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class ARMMachineFunctionGeneratorTest
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: public MachineFunctionGeneratorBaseTest {
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protected:
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ARMMachineFunctionGeneratorTest()
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: MachineFunctionGeneratorBaseTest("armv7-none-linux-gnueabi", "") {}
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static void SetUpTestCase() {
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LLVMInitializeARMTargetInfo();
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LLVMInitializeARMTargetMC();
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LLVMInitializeARMTarget();
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LLVMInitializeARMAsmPrinter();
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}
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};
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TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunction) {
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Check(ExegesisTarget::getDefault(), {}, llvm::MCInst(), 0x1e, 0xff, 0x2f,
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0xe1);
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}
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TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunctionADDrr) {
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Check(ExegesisTarget::getDefault(), {llvm::ARM::R0},
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MCInstBuilder(llvm::ARM::ADDrr)
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.addReg(llvm::ARM::R0)
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.addReg(llvm::ARM::R0)
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.addReg(llvm::ARM::R0)
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.addImm(llvm::ARMCC::AL)
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.addReg(0)
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.addReg(0),
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0x00, 0x00, 0x80, 0xe0, 0x1e, 0xff, 0x2f, 0xe1);
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}
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} // namespace
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} // namespace exegesis
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