536095a27c
Our actual lowering for i1 reductions uses ctpop combined with possibly a vector negate and possibly a logic op afterwards. I believe ctpop to be low cost on all reasonable hardware. The default costing implementation here was returning quite inconsistent costs. and/or were returning very high costs (because we seem to think moving into scalar registers is very expensive?) and others were returning lower but still too high (because of the assumed tree reduce strategy). While we should probably improve the generic costing strategy for i1 vectors, let's start by fixing the immediate problem. Differential Revision: https://reviews.llvm.org/D127511
468 lines
17 KiB
C++
468 lines
17 KiB
C++
//===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetTransformInfo.h"
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#include "MCTargetDesc/RISCVMatInt.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include <cmath>
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using namespace llvm;
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#define DEBUG_TYPE "riscvtti"
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static cl::opt<unsigned> RVVRegisterWidthLMUL(
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"riscv-v-register-bit-width-lmul",
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cl::desc(
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"The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
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"by autovectorized code. Fractional LMULs are not supported."),
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cl::init(1), cl::Hidden);
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InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind) {
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assert(Ty->isIntegerTy() &&
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"getIntImmCost can only estimate cost of materialising integers");
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// We have a Zero register, so 0 is always free.
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if (Imm == 0)
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return TTI::TCC_Free;
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// Otherwise, we check how many instructions it will take to materialise.
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const DataLayout &DL = getDataLayout();
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return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty),
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getST()->getFeatureBits());
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}
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InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind,
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Instruction *Inst) {
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assert(Ty->isIntegerTy() &&
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"getIntImmCost can only estimate cost of materialising integers");
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// We have a Zero register, so 0 is always free.
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if (Imm == 0)
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return TTI::TCC_Free;
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// Some instructions in RISC-V can take a 12-bit immediate. Some of these are
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// commutative, in others the immediate comes from a specific argument index.
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bool Takes12BitImm = false;
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unsigned ImmArgIdx = ~0U;
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switch (Opcode) {
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case Instruction::GetElementPtr:
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// Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
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// split up large offsets in GEP into better parts than ConstantHoisting
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// can.
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return TTI::TCC_Free;
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case Instruction::And:
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// zext.h
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if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
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return TTI::TCC_Free;
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// zext.w
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if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
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return TTI::TCC_Free;
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LLVM_FALLTHROUGH;
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case Instruction::Add:
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case Instruction::Or:
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case Instruction::Xor:
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case Instruction::Mul:
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Takes12BitImm = true;
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break;
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case Instruction::Sub:
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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Takes12BitImm = true;
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ImmArgIdx = 1;
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break;
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default:
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break;
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}
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if (Takes12BitImm) {
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// Check immediate is the correct argument...
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if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
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// ... and fits into the 12-bit immediate.
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if (Imm.getMinSignedBits() <= 64 &&
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getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
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return TTI::TCC_Free;
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}
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}
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// Otherwise, use the full materialisation cost.
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return getIntImmCost(Imm, Ty, CostKind);
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}
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// By default, prevent hoisting.
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return TTI::TCC_Free;
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}
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InstructionCost
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RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind) {
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// Prevent hoisting in unknown cases.
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return TTI::TCC_Free;
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}
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TargetTransformInfo::PopcntSupportKind
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RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return ST->hasStdExtZbb() ? TTI::PSK_FastHardware : TTI::PSK_Software;
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}
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bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
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// Currently, the ExpandReductions pass can't expand scalable-vector
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// reductions, but we still request expansion as RVV doesn't support certain
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// reductions and the SelectionDAG can't legalize them either.
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switch (II->getIntrinsicID()) {
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default:
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return false;
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// These reductions have no equivalent in RVV
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case Intrinsic::vector_reduce_mul:
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case Intrinsic::vector_reduce_fmul:
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return true;
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}
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}
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Optional<unsigned> RISCVTTIImpl::getMaxVScale() const {
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// There is no assumption of the maximum vector length in V specification.
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// We use the value specified by users as the maximum vector length.
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// This function will use the assumed maximum vector length to get the
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// maximum vscale for LoopVectorizer.
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// If users do not specify the maximum vector length, we have no way to
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// know whether the LoopVectorizer is safe to do or not.
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// We only consider to use single vector register (LMUL = 1) to vectorize.
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unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits();
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if (ST->hasVInstructions() && MaxVectorSizeInBits != 0)
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return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock;
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return BaseT::getMaxVScale();
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}
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TypeSize
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RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
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unsigned LMUL = PowerOf2Floor(
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std::max<unsigned>(std::min<unsigned>(RVVRegisterWidthLMUL, 8), 1));
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switch (K) {
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case TargetTransformInfo::RGK_Scalar:
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return TypeSize::getFixed(ST->getXLen());
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case TargetTransformInfo::RGK_FixedWidthVector:
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return TypeSize::getFixed(
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ST->hasVInstructions() ? LMUL * ST->getMinRVVVectorSizeInBits() : 0);
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case TargetTransformInfo::RGK_ScalableVector:
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return TypeSize::getScalable(
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ST->hasVInstructions() ? LMUL * RISCV::RVVBitsPerBlock : 0);
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}
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llvm_unreachable("Unsupported register kind");
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}
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InstructionCost RISCVTTIImpl::getSpliceCost(VectorType *Tp, int Index) {
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std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
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unsigned Cost = 2; // vslidedown+vslideup.
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// TODO: LMUL should increase cost.
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// TODO: Multiplying by LT.first implies this legalizes into multiple copies
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// of similar code, but I think we expand through memory.
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return Cost * LT.first;
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}
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InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
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VectorType *Tp, ArrayRef<int> Mask,
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int Index, VectorType *SubTp,
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ArrayRef<const Value *> Args) {
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if (isa<ScalableVectorType>(Tp)) {
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std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
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switch (Kind) {
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default:
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// Fallthrough to generic handling.
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// TODO: Most of these cases will return getInvalid in generic code, and
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// must be implemented here.
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break;
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case TTI::SK_Broadcast: {
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return LT.first * 1;
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}
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case TTI::SK_Splice:
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return getSpliceCost(Tp, Index);
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case TTI::SK_Reverse:
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// Most of the cost here is producing the vrgather index register
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// Example sequence:
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// csrr a0, vlenb
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// srli a0, a0, 3
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// addi a0, a0, -1
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// vsetvli a1, zero, e8, mf8, ta, mu (ignored)
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// vid.v v9
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// vrsub.vx v10, v9, a0
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// vrgather.vv v9, v8, v10
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return LT.first * 6;
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}
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}
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return BaseT::getShuffleCost(Kind, Tp, Mask, Index, SubTp);
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}
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InstructionCost
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RISCVTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind) {
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if (!isa<ScalableVectorType>(Src))
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return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
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CostKind);
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return getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
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}
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InstructionCost RISCVTTIImpl::getGatherScatterOpCost(
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unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
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Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
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if (CostKind != TTI::TCK_RecipThroughput)
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return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
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Alignment, CostKind, I);
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if ((Opcode == Instruction::Load &&
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!isLegalMaskedGather(DataTy, Align(Alignment))) ||
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(Opcode == Instruction::Store &&
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!isLegalMaskedScatter(DataTy, Align(Alignment))))
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return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
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Alignment, CostKind, I);
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// FIXME: Only supporting fixed vectors for now.
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if (!isa<FixedVectorType>(DataTy))
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return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
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Alignment, CostKind, I);
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auto *VTy = cast<FixedVectorType>(DataTy);
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unsigned NumLoads = VTy->getNumElements();
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InstructionCost MemOpCost =
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getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I);
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return NumLoads * MemOpCost;
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}
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InstructionCost
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RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind) {
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auto *RetTy = ICA.getReturnType();
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switch (ICA.getID()) {
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// TODO: add more intrinsic
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case Intrinsic::experimental_stepvector: {
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unsigned Cost = 1; // vid
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auto LT = TLI->getTypeLegalizationCost(DL, RetTy);
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return Cost + (LT.first - 1);
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}
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default:
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break;
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}
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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}
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InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src,
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TTI::CastContextHint CCH,
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TTI::TargetCostKind CostKind,
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const Instruction *I) {
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if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
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// FIXME: Need to compute legalizing cost for illegal types.
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if (!isTypeLegal(Src) || !isTypeLegal(Dst))
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return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
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// Skip if element size of Dst or Src is bigger than ELEN.
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if (Src->getScalarSizeInBits() > ST->getELEN() ||
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Dst->getScalarSizeInBits() > ST->getELEN())
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return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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// FIXME: Need to consider vsetvli and lmul.
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int PowDiff = (int)Log2_32(Dst->getScalarSizeInBits()) -
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(int)Log2_32(Src->getScalarSizeInBits());
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switch (ISD) {
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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return 1;
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case ISD::TRUNCATE:
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case ISD::FP_EXTEND:
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case ISD::FP_ROUND:
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// Counts of narrow/widen instructions.
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return std::abs(PowDiff);
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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if (std::abs(PowDiff) <= 1)
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return 1;
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// Backend could lower (v[sz]ext i8 to double) to vfcvt(v[sz]ext.f8 i8),
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// so it only need two conversion.
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if (Src->isIntOrIntVectorTy())
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return 2;
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// Counts of narrow/widen instructions.
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return std::abs(PowDiff);
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}
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}
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return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
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}
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InstructionCost
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RISCVTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
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bool IsUnsigned,
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TTI::TargetCostKind CostKind) {
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// FIXME: Only supporting fixed vectors for now.
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if (!isa<FixedVectorType>(Ty))
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return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
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if (!ST->useRVVForFixedLengthVectors())
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return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
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// Skip if scalar size of Ty is bigger than ELEN.
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if (Ty->getScalarSizeInBits() > ST->getELEN())
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return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
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std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
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if (Ty->getElementType()->isIntegerTy(1))
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// vcpop sequences, see vreduction-mask.ll. umax, smin actually only
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// cost 2, but we don't have enough info here so we slightly over cost.
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return (LT.first - 1) + 3;
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// IR Reduction is composed by two vmv and one rvv reduction instruction.
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InstructionCost BaseCost = 2;
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unsigned VL = cast<FixedVectorType>(Ty)->getNumElements();
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return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
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}
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InstructionCost
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RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *VTy,
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Optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind) {
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// FIXME: Only supporting fixed vectors for now.
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if (!isa<FixedVectorType>(VTy))
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return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
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if (!ST->useRVVForFixedLengthVectors())
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return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
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// Skip if scalar size of VTy is bigger than ELEN.
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if (VTy->getScalarSizeInBits() > ST->getELEN())
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return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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if (ISD != ISD::ADD && ISD != ISD::OR && ISD != ISD::XOR && ISD != ISD::AND &&
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ISD != ISD::FADD)
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return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
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std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, VTy);
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if (VTy->getElementType()->isIntegerTy(1))
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// vcpop sequences, see vreduction-mask.ll
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return (LT.first - 1) + (ISD == ISD::AND ? 3 : 2);
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// IR Reduction is composed by two vmv and one rvv reduction instruction.
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InstructionCost BaseCost = 2;
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unsigned VL = cast<FixedVectorType>(VTy)->getNumElements();
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if (TTI::requiresOrderedReduction(FMF))
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return (LT.first - 1) + BaseCost + VL;
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return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
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}
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void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE) {
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// TODO: More tuning on benchmarks and metrics with changes as needed
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// would apply to all settings below to enable performance.
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if (ST->enableDefaultUnroll())
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return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP, ORE);
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// Enable Upper bound unrolling universally, not dependant upon the conditions
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// below.
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UP.UpperBound = true;
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// Disable loop unrolling for Oz and Os.
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UP.OptSizeThreshold = 0;
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UP.PartialOptSizeThreshold = 0;
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if (L->getHeader()->getParent()->hasOptSize())
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return;
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SmallVector<BasicBlock *, 4> ExitingBlocks;
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L->getExitingBlocks(ExitingBlocks);
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LLVM_DEBUG(dbgs() << "Loop has:\n"
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<< "Blocks: " << L->getNumBlocks() << "\n"
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<< "Exit blocks: " << ExitingBlocks.size() << "\n");
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// Only allow another exit other than the latch. This acts as an early exit
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// as it mirrors the profitability calculation of the runtime unroller.
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if (ExitingBlocks.size() > 2)
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return;
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// Limit the CFG of the loop body for targets with a branch predictor.
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// Allowing 4 blocks permits if-then-else diamonds in the body.
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if (L->getNumBlocks() > 4)
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return;
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// Don't unroll vectorized loops, including the remainder loop
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if (getBooleanLoopAttribute(L, "llvm.loop.isvectorized"))
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return;
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// Scan the loop: don't unroll loops with calls as this could prevent
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// inlining.
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InstructionCost Cost = 0;
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for (auto *BB : L->getBlocks()) {
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for (auto &I : *BB) {
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// Initial setting - Don't unroll loops containing vectorized
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// instructions.
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if (I.getType()->isVectorTy())
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return;
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if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
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if (const Function *F = cast<CallBase>(I).getCalledFunction()) {
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if (!isLoweredToCall(F))
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continue;
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}
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return;
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}
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SmallVector<const Value *> Operands(I.operand_values());
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Cost +=
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getUserCost(&I, Operands, TargetTransformInfo::TCK_SizeAndLatency);
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}
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}
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LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n");
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UP.Partial = true;
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UP.Runtime = true;
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UP.UnrollRemainder = true;
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UP.UnrollAndJam = true;
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UP.UnrollAndJamInnerLoopThreshold = 60;
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// Force unrolling small loops can be very useful because of the branch
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// taken cost of the backedge.
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if (Cost < 12)
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UP.Force = true;
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}
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void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP) {
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BaseT::getPeelingPreferences(L, SE, PP);
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}
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unsigned RISCVTTIImpl::getRegUsageForType(Type *Ty) {
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TypeSize Size = Ty->getPrimitiveSizeInBits();
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if (Ty->isVectorTy()) {
|
|
if (Size.isScalable() && ST->hasVInstructions())
|
|
return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
|
|
|
|
if (ST->useRVVForFixedLengthVectors())
|
|
return divideCeil(Size, ST->getMinRVVVectorSizeInBits());
|
|
}
|
|
|
|
return BaseT::getRegUsageForType(Ty);
|
|
}
|