b04672cade
Summary: Without these patterns we would generate a complete LL/SC sequence. This would be problematic for memory regions marked as WRITE-only or READ-only, as the instructions LL/SC would read/write to the protected memory regions correspondingly. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14397 llvm-svn: 252293
43 lines
1001 B
LLVM
43 lines
1001 B
LLVM
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64
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; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64
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define i8 @load_i8(i8* %ptr) {
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; ALL-LABEL: load_i8
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; ALL: lb $2, 0($4)
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; ALL: sync
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%val = load atomic i8, i8* %ptr acquire, align 1
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ret i8 %val
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}
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define i16 @load_i16(i16* %ptr) {
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; ALL-LABEL: load_i16
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; ALL: lh $2, 0($4)
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; ALL: sync
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%val = load atomic i16, i16* %ptr acquire, align 2
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ret i16 %val
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}
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define i32 @load_i32(i32* %ptr) {
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; ALL-LABEL: load_i32
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; ALL: lw $2, 0($4)
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; ALL: sync
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%val = load atomic i32, i32* %ptr acquire, align 4
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ret i32 %val
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}
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define i64 @load_i64(i64* %ptr) {
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; M64-LABEL: load_i64
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; M64: ld $2, 0($4)
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; M64: sync
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%val = load atomic i64, i64* %ptr acquire, align 8
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ret i64 %val
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}
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