3ad5765e23
Check that all partial reductions in a chain are only used by other partial reductions with the same scale factor. Otherwise we end up creating users of scaled reductions where the types of the other operands don't match. A similar issue was addressed in https://github.com/llvm/llvm-project/pull/158603, but misses the chained cases. Fixes https://github.com/llvm/llvm-project/issues/162530. PR: https://github.com/llvm/llvm-project/pull/162822
98 lines
5.0 KiB
LLVM
98 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
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; RUN: opt --mattr=+neon,+dotprod -passes=loop-vectorize -force-vector-interleave=1 -enable-epilogue-vectorization=false -S %s | FileCheck %s --check-prefixes=CHECK-NEON
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target triple = "arm64-apple-macosx"
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define i32 @red_extended_add_incomplete_chain(ptr %start, ptr %end, i32 %offset) {
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; CHECK-NEON-LABEL: define i32 @red_extended_add_incomplete_chain(
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; CHECK-NEON-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEON-NEXT: [[ENTRY:.*]]:
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; CHECK-NEON-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
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; CHECK-NEON-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
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; CHECK-NEON-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
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; CHECK-NEON-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
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; CHECK-NEON-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
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; CHECK-NEON-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK-NEON: [[VECTOR_PH]]:
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; CHECK-NEON-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 16
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; CHECK-NEON-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
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; CHECK-NEON-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]
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; CHECK-NEON-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[OFFSET]], i64 0
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; CHECK-NEON-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i32> [[BROADCAST_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
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; CHECK-NEON-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK-NEON: [[VECTOR_BODY]]:
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; CHECK-NEON-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEON-NEXT: [[VEC_PHI:%.*]] = phi <16 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEON-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[INDEX]]
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; CHECK-NEON-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[NEXT_GEP]], align 1
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; CHECK-NEON-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i32>
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; CHECK-NEON-NEXT: [[TMP4:%.*]] = add <16 x i32> [[VEC_PHI]], [[TMP3]]
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; CHECK-NEON-NEXT: [[TMP5]] = add <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]]
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; CHECK-NEON-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
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; CHECK-NEON-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEON-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK-NEON: [[MIDDLE_BLOCK]]:
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; CHECK-NEON-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP5]])
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; CHECK-NEON-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
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; CHECK-NEON-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK-NEON: [[SCALAR_PH]]:
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; CHECK-NEON-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]
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; CHECK-NEON-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEON-NEXT: br label %[[LOOP:.*]]
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; CHECK-NEON: [[LOOP]]:
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; CHECK-NEON-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[GEP_IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEON-NEXT: [[RED:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEON-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV]], align 1
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; CHECK-NEON-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32
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; CHECK-NEON-NEXT: [[ADD:%.*]] = add i32 [[RED]], [[L_EXT]]
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; CHECK-NEON-NEXT: [[RED_NEXT]] = add i32 [[ADD]], [[OFFSET]]
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; CHECK-NEON-NEXT: [[GEP_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 1
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; CHECK-NEON-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV]], [[END]]
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; CHECK-NEON-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK-NEON: [[EXIT]]:
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; CHECK-NEON-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i32 [ [[RED_NEXT]], %[[LOOP]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEON-NEXT: ret i32 [[RED_NEXT_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ]
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%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
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%l = load i8, ptr %ptr.iv, align 1
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%l.ext = zext i8 %l to i32
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%add = add i32 %red, %l.ext
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%red.next = add i32 %add, %offset
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%gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1
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%ec = icmp eq ptr %ptr.iv, %end
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br i1 %ec, label %exit, label %loop
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exit:
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ret i32 %red.next
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}
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define i16 @test_incomplete_chain_without_mul(ptr noalias %dst, ptr %A, ptr %B) #0 {
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%red = phi i16 [ 0, %entry ], [ %red.next, %loop ]
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%l.a = load i8, ptr %A, align 1
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%a.ext = zext i8 %l.a to i16
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store i16 %a.ext, ptr %dst, align 2
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%l.b = load i8, ptr %B, align 1
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%b.ext = zext i8 %l.b to i16
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%add = add i16 %red, %b.ext
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%add.1 = add i16 %add, %a.ext
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%red.next = add i16 %add.1, %b.ext
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%iv.next = add i64 %iv, 1
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%ec = icmp ult i64 %iv, 1024
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br i1 %ec, label %loop, label %exit
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exit:
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ret i16 %red.next
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}
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attributes #0 = { "target-cpu"="grace" }
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