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llvm-project/llvm/test/Transforms/VectorCombine
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hanbeom 50ba89a22e
[VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (#126408)
insertelt DestVec, (fneg (extractelt SrcVec, Index)), Index 
-> shuffle DestVec, (shuffle (fneg SrcVec), poison, SrcMask), Mask

In previous, the above transform was only possible if the Extract/Insert
Index was the same; this patch makes the above transform possible
even if the two indexes are different.

Proof: https://alive2.llvm.org/ce/z/aDfdyG
Fixes: https://github.com/llvm/llvm-project/issues/125675
2025-11-07 18:35:40 +00:00
..
AArch64
[BasicTTI] Only split vectors with even element counts in getCastInstrCost (#166528)
2025-11-06 12:45:42 +00:00
AMDGPU
[AMDGPU] NFC, move testcase, only test output of promote-alloca with vector-combine (#166289)
2025-11-03 22:21:26 -05:00
ARM
…
Hexagon
…
PowerPC
[VectorCombine] Fix scalarizeExtExtract for big-endian (#157962)
2025-09-15 10:08:16 +00:00
RISCV
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SPIRV
…
X86
[VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (#126408)
2025-11-07 18:35:40 +00:00
alias.ll
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binop-scalarize.ll
…
fold-binop-of-reductions.ll
…
fold-shuffle-chains-to-reduce.ll
…
intrinsic-scalarize.ll
[IR] NFC: Remove 'experimental' from partial.reduce.add intrinsic (#158637)
2025-09-17 11:44:47 +01:00
load-insert-store.ll
…
load-shufflevector.ll
…
narrow-phi-of-shuffles.ll
…
pr88796.ll
…
pr132563.ll
…
pr157335.ll
…
unary-op-scalarize.ll
…
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