Allen d1006315b5
[AArch64] Lower for power of 2 signed divides with scalar type (#97879)
Expected same assemble for code which doesn't use sve registers when we
compile it with/without -msve-vector-bits=256.

Fix https://github.com/llvm/llvm-project/issues/97821
2024-07-10 21:52:09 +08:00
..
2023-08-08 21:59:53 +01:00

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.