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llvm-project/llvm/test/CodeGen
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Simon Pilgrim b8652fbcbb [X86] Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) (RECOMMITTED) 
As noticed on PR39174, if we're extracting a single non-constant bit index, then try to use BT+SETCC instead to avoid messing around moving the shift amount to the ECX register, using slow x86 shift ops etc.

Recommitted with a fix to ensure we zext/trunc the SETCC result to the original type.

Differential Revision: https://reviews.llvm.org/D122891
2022-04-01 16:59:06 +01:00
..
AArch64
[AArch64] Set MaxBytesForLoopAlignment for more targets
2022-03-31 11:37:11 +01:00
AMDGPU
[AMDGPU] Only count global-to-global as indirect accesses
2022-04-01 13:48:13 +01:00
ARC
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ARM
ARM/GlobalISel: Get pointer type from value instead of getPointerSize
2022-03-31 16:46:23 -04:00
AVR
[AVR] Optimize int16 airthmetic right shift for shift amount 7/14/15
2022-03-26 06:53:27 +00:00
BPF
BPF: support inlining __builtin_memcmp intrinsic call
2022-03-29 15:03:26 -07:00
CSKY
[CSKY] Add CSKYTargetObjectFile to support exception handling
2022-03-29 16:05:30 +08:00
Generic
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Hexagon
[Hexagon] Create an intrinsic to profile using a custom handler
2022-03-28 10:31:41 -05:00
Inputs
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Lanai
…
LoongArch
[LoongArch] Construct codegen infra and generate first add instruction.
2022-03-31 11:57:07 +08:00
M68k
m68k: Support bit shifts on 64-bit integers
2022-02-12 06:11:49 +08:00
Mips
[Mips] support "sp" named register
2022-03-03 13:53:36 -08:00
MIR
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
MLRegalloc
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MSP430
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NVPTX
[NVPTX] Fix poorly designed assertion introduced in D120129
2022-03-28 17:34:58 +03:00
PowerPC
[PowerPC] Fix lowering of byval parameters for sizes greater than 8 bytes.
2022-03-31 15:12:46 -05:00
RISCV
[RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub
2022-04-01 03:09:50 +00:00
SPARC
[Sparc] Add tail call support
2022-03-08 13:50:54 +01:00
SystemZ
[SystemZ] generate full checks for tests; NFC
2022-03-30 08:37:15 -04:00
Thumb
[ARM] Fix 8-bit immediate overflow in the instruction of segmented stack prologue.
2022-03-10 15:15:24 -08:00
Thumb2
[ARM] Fix 8-bit immediate overflow in the instruction of segmented stack prologue.
2022-03-10 15:15:24 -08:00
VE
[VP] Preserve address space of pointer for strided load/store intrinsics.
2022-03-22 09:52:54 -07:00
WebAssembly
[WebAssembly] Always emit functype directives for defined functions
2022-03-22 09:24:58 +00:00
WinCFGuard
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WinEH
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X86
[X86] Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) (RECOMMITTED)
2022-04-01 16:59:06 +01:00
XCore
[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
2022-02-18 16:10:56 +00:00