8728c5f2db
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. llvm-svn: 310258
189 lines
7.3 KiB
LLVM
189 lines
7.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}simple_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF]]
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; GCN: s_and_b64 exec, exec, vcc
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; GCN-NEXT: ; mask branch [[ENDIF]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @simple_nested_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = icmp ugt i32 %tmp, 1
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br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.outer.end, label %bb.inner.then
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bb.inner.then: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 1
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%tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 1, i32 addrspace(1)* %tmp9, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb.outer.then, %bb.inner.then, %bb
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ret void
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}
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; GCN-LABEL: {{^}}uncollapsable_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_INNER:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_INNER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @uncollapsable_nested_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = icmp ugt i32 %tmp, 1
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br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.inner.end, label %bb.inner.then
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bb.inner.then: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 1
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%tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 1, i32 addrspace(1)* %tmp8, align 4
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br label %bb.inner.end
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bb.inner.end: ; preds = %bb.inner.then, %bb.outer.then
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%tmp9 = add i32 %tmp, 2
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%tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp9
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store i32 2, i32 addrspace(1)* %tmp10, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb.inner.then, %bb
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ret void
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}
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; GCN-LABEL: {{^}}nested_if_if_else:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
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; GCN-NEXT: ; mask branch [[THEN_INNER:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[THEN_INNER]]:
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; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_INNER3:s\[[0-9:]+\]]], [[SAVEEXEC_INNER2]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER]]
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @nested_if_if_else(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp1, align 4
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%tmp2 = icmp ugt i32 %tmp, 1
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br i1 %tmp2, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.then, label %bb.else
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bb.then: ; preds = %bb.outer.then
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%tmp3 = add i32 %tmp, 1
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp3
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store i32 1, i32 addrspace(1)* %tmp4, align 4
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br label %bb.outer.end
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bb.else: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 2
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%tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 2, i32 addrspace(1)* %tmp9, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb, %bb.then, %bb.else
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ret void
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}
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; GCN-LABEL: {{^}}nested_if_else_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: ; mask branch [[THEN_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[THEN_OUTER]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[THEN_OUTER_FLOW:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
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; GCN-NEXT: {{^}}[[THEN_OUTER]]:
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; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_OUTER3:s\[[0-9:]+\]]], [[SAVEEXEC_OUTER2]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_THEN:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_INNER_OUTER_THEN:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_INNER_OUTER_THEN]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_THEN]]
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER3]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @nested_if_else_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp1, align 4
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%cc1 = icmp ugt i32 %tmp, 1
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br i1 %cc1, label %bb.outer.then, label %bb.outer.else
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bb.outer.then:
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 1
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store i32 1, i32 addrspace(1)* %tmp2, align 4
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%cc2 = icmp eq i32 %tmp, 2
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br i1 %cc2, label %bb.inner.then, label %bb.outer.end
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bb.inner.then:
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%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 2
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store i32 2, i32 addrspace(1)* %tmp3, align 4
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br label %bb.outer.end
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bb.outer.else:
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 3
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store i32 3, i32 addrspace(1)* %tmp4, align 4
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%cc3 = icmp eq i32 %tmp, 2
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br i1 %cc3, label %bb.inner.then2, label %bb.outer.end
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bb.inner.then2:
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 4
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store i32 4, i32 addrspace(1)* %tmp5, align 4
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br label %bb.outer.end
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bb.outer.end:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone speculatable }
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