572fc7d2fd
This patch adds an AArch64 specific PostRA MachineScheduler to try to schedule STP Q's to the same base-address in ascending order of offsets. We have found this to improve performance on Neoverse N1 and should not hurt other AArch64 cores. Differential Revision: https://reviews.llvm.org/D125377
34 lines
1.0 KiB
C++
34 lines
1.0 KiB
C++
//===- AArch64MachineScheduler.h - Custom AArch64 MI scheduler --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Custom AArch64 MI scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINESCHEDULER_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINESCHEDULER_H
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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/// A MachineSchedStrategy implementation for AArch64 post RA scheduling.
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class AArch64PostRASchedStrategy : public PostGenericScheduler {
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public:
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AArch64PostRASchedStrategy(const MachineSchedContext *C) :
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PostGenericScheduler(C) {}
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protected:
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bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override;
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};
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} // end namespace llvm
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#endif
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