28233408a2
When using Greedy Register Allocation, there are times where early-clobber values are ignored, and assigned the same register. This is illeagal behaviour for these intructions. To get around this, using Pseudo instructions for early-clobber registers gives them a definition and allows Greedy to assign them to a different register. This then meets the ARM Architecture Reference Manual and matches the defined behaviour. This patch takes the existing RISC-V patch and makes it target independent, then adds support for the ARM Architecture. Doing this will ensure early-clobber restraints are followed when using the ARM Architecture. Making the pass target independent will also open up possibility that support other architectures can be added in the future.
572 lines
19 KiB
C++
572 lines
19 KiB
C++
//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMFrameLowering.h"
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#include "ARMISelLowering.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSelectionDAGInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/TargetParser/Triple.h"
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#include <bitset>
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#include <memory>
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "ARMGenSubtargetInfo.inc"
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namespace llvm {
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class ARMBaseTargetMachine;
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class GlobalValue;
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class StringRef;
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class ARMSubtarget : public ARMGenSubtargetInfo {
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protected:
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enum ARMProcFamilyEnum {
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Others,
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CortexA12,
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CortexA15,
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CortexA17,
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CortexA32,
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CortexA35,
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CortexA5,
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CortexA53,
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CortexA55,
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CortexA57,
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CortexA7,
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CortexA72,
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CortexA73,
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CortexA75,
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CortexA76,
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CortexA77,
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CortexA78,
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CortexA78C,
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CortexA710,
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CortexA8,
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CortexA9,
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CortexM3,
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CortexM7,
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CortexM52,
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CortexR4,
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CortexR4F,
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CortexR5,
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CortexR52,
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CortexR7,
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CortexX1,
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CortexX1C,
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Exynos,
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Krait,
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Kryo,
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NeoverseN1,
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NeoverseN2,
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NeoverseV1,
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Swift
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};
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enum ARMProcClassEnum {
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None,
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AClass,
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MClass,
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RClass
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};
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enum ARMArchEnum {
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ARMv4,
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ARMv4t,
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ARMv5,
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ARMv5t,
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ARMv5te,
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ARMv5tej,
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ARMv6,
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ARMv6k,
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ARMv6kz,
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ARMv6m,
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ARMv6sm,
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ARMv6t2,
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ARMv7a,
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ARMv7em,
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ARMv7m,
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ARMv7r,
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ARMv7ve,
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ARMv81a,
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ARMv82a,
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ARMv83a,
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ARMv84a,
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ARMv85a,
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ARMv86a,
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ARMv87a,
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ARMv88a,
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ARMv89a,
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ARMv8a,
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ARMv8mBaseline,
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ARMv8mMainline,
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ARMv8r,
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ARMv81mMainline,
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ARMv9a,
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ARMv91a,
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ARMv92a,
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ARMv93a,
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ARMv94a,
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ARMv95a,
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};
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public:
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/// What kind of timing do load multiple/store multiple instructions have.
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enum ARMLdStMultipleTiming {
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/// Can load/store 2 registers/cycle.
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DoubleIssue,
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/// Can load/store 2 registers/cycle, but needs an extra cycle if the access
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/// is not 64-bit aligned.
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DoubleIssueCheckUnalignedAccess,
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/// Can load/store 1 register/cycle.
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SingleIssue,
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/// Can load/store 1 register/cycle, but needs an extra cycle for address
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/// computation and potentially also for register writeback.
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SingleIssuePlusExtras,
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};
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protected:
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// Bool members corresponding to the SubtargetFeatures defined in tablegen
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool ATTRIBUTE = DEFAULT;
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#include "ARMGenSubtargetInfo.inc"
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/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
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ARMProcFamilyEnum ARMProcFamily = Others;
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/// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
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ARMProcClassEnum ARMProcClass = None;
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/// ARMArch - ARM architecture
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ARMArchEnum ARMArch = ARMv4t;
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/// UseMulOps - True if non-microcoded fused integer multiply-add and
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/// multiply-subtract instructions should be used.
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bool UseMulOps = false;
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/// SupportsTailCall - True if the OS supports tail call. The dynamic linker
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/// must be able to synthesize call stubs for interworking between ARM and
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/// Thumb.
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bool SupportsTailCall = false;
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/// RestrictIT - If true, the subtarget disallows generation of complex IT
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/// blocks.
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bool RestrictIT = false;
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/// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
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bool UseSjLjEH = false;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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Align stackAlignment = Align(4);
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/// CPUString - String name of used CPU.
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std::string CPUString;
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unsigned MaxInterleaveFactor = 1;
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/// Clearance before partial register updates (in number of instructions)
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unsigned PartialUpdateClearance = 0;
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/// What kind of timing do load multiple/store multiple have (double issue,
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/// single issue etc).
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ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
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/// The adjustment that we need to apply to get the operand latency from the
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/// operand cycle returned by the itinerary data for pre-ISel operands.
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int PreISelOperandLatencyAdjustment = 2;
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/// What alignment is preferred for loop bodies and functions, in log2(bytes).
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unsigned PrefLoopLogAlignment = 0;
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/// The cost factor for MVE instructions, representing the multiple beats an
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// instruction can take. The default is 2, (set in initSubtargetFeatures so
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// that we can use subtarget features less than 2).
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unsigned MVEVectorCostFactor = 0;
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/// OptMinSize - True if we're optimising for minimum code size, equal to
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/// the function attribute.
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bool OptMinSize = false;
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/// IsLittle - The target is Little Endian
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bool IsLittle;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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/// SchedModel - Processor specific instruction costs.
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MCSchedModel SchedModel;
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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/// Options passed via command line that could influence the target
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const TargetOptions &Options;
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const ARMBaseTargetMachine &TM;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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const ARMBaseTargetMachine &TM, bool IsLittle,
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bool MinSize = false);
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/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const {
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return 64;
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}
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/// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
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/// that still makes it profitable to inline a llvm.memcpy as a Tail
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/// Predicated loop.
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/// This threshold should only be used for constant size inputs.
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unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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/// initializeSubtargetDependencies - Initializes using a CPU and feature string
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/// so that we can use initializer lists for subtarget initialization.
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ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const ARMBaseInstrInfo *getInstrInfo() const override {
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return InstrInfo.get();
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}
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const ARMTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const ARMFrameLowering *getFrameLowering() const override {
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return FrameLowering.get();
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}
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const ARMBaseRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo->getRegisterInfo();
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}
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/// The correct instructions have been implemented to initialize undef
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/// registers, therefore the ARM Architecture is supported by the Init Undef
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/// Pass. This will return true as the pass needs to be supported for all
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/// types of instructions. The pass will then perform more checks to ensure it
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/// should be applying the Pseudo Instructions.
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bool supportsInitUndef() const override { return true; }
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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private:
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ARMSelectionDAGInfo TSInfo;
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// Either Thumb1FrameLowering or ARMFrameLowering.
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std::unique_ptr<ARMFrameLowering> FrameLowering;
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// Either Thumb1InstrInfo or Thumb2InstrInfo.
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std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
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ARMTargetLowering TLInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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void initializeEnvironment();
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void initSubtargetFeatures(StringRef CPU, StringRef FS);
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ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
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std::bitset<8> CoprocCDE = {};
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public:
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// Getters for SubtargetFeatures defined in tablegen
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool GETTER() const { return ATTRIBUTE; }
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#include "ARMGenSubtargetInfo.inc"
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/// @{
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/// These functions are obsolete, please consider adding subtarget features
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/// or properties instead of calling them.
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bool isCortexA5() const { return ARMProcFamily == CortexA5; }
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bool isCortexA7() const { return ARMProcFamily == CortexA7; }
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bool isCortexA8() const { return ARMProcFamily == CortexA8; }
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bool isCortexA9() const { return ARMProcFamily == CortexA9; }
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bool isCortexA15() const { return ARMProcFamily == CortexA15; }
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bool isSwift() const { return ARMProcFamily == Swift; }
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bool isCortexM3() const { return ARMProcFamily == CortexM3; }
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bool isCortexM7() const { return ARMProcFamily == CortexM7; }
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bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
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bool isCortexR5() const { return ARMProcFamily == CortexR5; }
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bool isKrait() const { return ARMProcFamily == Krait; }
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/// @}
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bool hasARMOps() const { return !NoARM; }
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bool useNEONForSinglePrecisionFP() const {
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return hasNEON() && hasNEONForFP();
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}
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bool hasVFP2Base() const { return hasVFPv2SP(); }
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bool hasVFP3Base() const { return hasVFPv3D16SP(); }
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bool hasVFP4Base() const { return hasVFPv4D16SP(); }
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bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); }
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bool hasAnyDataBarrier() const {
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return HasDataBarrier || (hasV6Ops() && !isThumb());
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}
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bool useMulOps() const { return UseMulOps; }
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bool useFPVMLx() const { return !SlowFPVMLx; }
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bool useFPVFMx() const {
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return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
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}
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bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
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bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
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bool useSjLjEH() const { return UseSjLjEH; }
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bool hasBaseDSP() const {
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if (isThumb())
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return hasThumb2() && hasDSP();
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else
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return hasV5TEOps();
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}
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/// Return true if the CPU supports any kind of instruction fusion.
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bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetIOS() const { return TargetTriple.isiOS(); }
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bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
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bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
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bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
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bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
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bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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// ARM EABI is the bare-metal EABI described in ARM ABI documents and
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// can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
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// FIXME: Add a flag for bare-metal for that target and set Triple::EABI
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// even for GNUEABI, so we can make a distinction here and still conform to
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// the EABI on GNU (and Android) mode. This requires change in Clang, too.
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// FIXME: The Darwin exception is temporary, while we move users to
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// "*-*-*-macho" triples as quickly as possible.
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bool isTargetAEABI() const {
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return (TargetTriple.getEnvironment() == Triple::EABI ||
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TargetTriple.getEnvironment() == Triple::EABIHF) &&
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!isTargetDarwin() && !isTargetWindows();
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}
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bool isTargetGNUAEABI() const {
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return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
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TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
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!isTargetDarwin() && !isTargetWindows();
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}
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bool isTargetMuslAEABI() const {
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return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
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TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
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TargetTriple.getEnvironment() == Triple::OpenHOS) &&
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!isTargetDarwin() && !isTargetWindows();
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}
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// ARM Targets that support EHABI exception handling standard
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// Darwin uses SjLj. Other targets might need more checks.
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bool isTargetEHABICompatible() const {
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return TargetTriple.isTargetEHABICompatible();
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}
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bool isTargetHardFloat() const;
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bool isReadTPSoft() const {
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return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW());
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}
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bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
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bool isXRaySupported() const override;
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bool isAPCS_ABI() const;
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bool isAAPCS_ABI() const;
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bool isAAPCS16_ABI() const;
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bool isROPI() const;
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bool isRWPI() const;
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bool useMachineScheduler() const { return UseMISched; }
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bool useMachinePipeliner() const { return UseMIPipeliner; }
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bool hasMinSize() const { return OptMinSize; }
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bool isThumb1Only() const { return isThumb() && !hasThumb2(); }
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bool isThumb2() const { return isThumb() && hasThumb2(); }
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bool isMClass() const { return ARMProcClass == MClass; }
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bool isRClass() const { return ARMProcClass == RClass; }
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bool isAClass() const { return ARMProcClass == AClass; }
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bool isR9Reserved() const {
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return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
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}
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MCPhysReg getFramePointerReg() const {
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if (isTargetDarwin() ||
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(!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))
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return ARM::R7;
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return ARM::R11;
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}
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/// Returns true if the frame setup is split into two separate pushes (first
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/// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
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/// to lr. This is always required on Thumb1-only targets, as the push and
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/// pop instructions can't access the high registers.
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bool splitFramePushPop(const MachineFunction &MF) const {
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if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress())
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return true;
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return (getFramePointerReg() == ARM::R7 &&
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MF.getTarget().Options.DisableFramePointerElim(MF)) ||
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isThumb1Only();
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}
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bool splitFramePointerPush(const MachineFunction &MF) const;
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bool useStride4VFPs() const;
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bool useMovt() const;
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bool supportsTailCall() const { return SupportsTailCall; }
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bool allowsUnalignedMem() const { return !StrictAlign; }
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bool restrictIT() const { return RestrictIT; }
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const std::string & getCPUString() const { return CPUString; }
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bool isLittle() const { return IsLittle; }
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unsigned getMispredictionPenalty() const;
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/// Returns true if machine scheduler should be enabled.
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bool enableMachineScheduler() const override;
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/// Returns true if machine pipeliner should be enabled.
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bool enableMachinePipeliner() const override;
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bool useDFAforSMS() const override;
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/// True for some subtargets at > -O0.
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bool enablePostRAScheduler() const override;
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/// True for some subtargets at > -O0.
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bool enablePostRAMachineScheduler() const override;
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|
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|
/// Check whether this subtarget wants to use subregister liveness.
|
|
bool enableSubRegLiveness() const override;
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|
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/// Enable use of alias analysis during code generation (during MI
|
|
/// scheduling, DAGCombine, etc.).
|
|
bool useAA() const override { return true; }
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|
|
|
/// getInstrItins - Return the instruction itineraries based on subtarget
|
|
/// selection.
|
|
const InstrItineraryData *getInstrItineraryData() const override {
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|
return &InstrItins;
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|
}
|
|
|
|
/// getStackAlignment - Returns the minimum alignment known to hold of the
|
|
/// stack frame on entry to the function and which must be maintained by every
|
|
/// function for this subtarget.
|
|
Align getStackAlignment() const { return stackAlignment; }
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|
|
|
// Returns the required alignment for LDRD/STRD instructions
|
|
Align getDualLoadStoreAlignment() const {
|
|
return Align(hasV7Ops() || allowsUnalignedMem() ? 4 : 8);
|
|
}
|
|
|
|
unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
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|
|
|
unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
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|
|
|
ARMLdStMultipleTiming getLdStMultipleTiming() const {
|
|
return LdStMultipleTiming;
|
|
}
|
|
|
|
int getPreISelOperandLatencyAdjustment() const {
|
|
return PreISelOperandLatencyAdjustment;
|
|
}
|
|
|
|
/// True if the GV will be accessed via an indirect symbol.
|
|
bool isGVIndirectSymbol(const GlobalValue *GV) const;
|
|
|
|
/// Returns the constant pool modifier needed to access the GV.
|
|
bool isGVInGOT(const GlobalValue *GV) const;
|
|
|
|
/// True if fast-isel is used.
|
|
bool useFastISel() const;
|
|
|
|
/// Returns the correct return opcode for the current feature set.
|
|
/// Use BX if available to allow mixing thumb/arm code, but fall back
|
|
/// to plain mov pc,lr on ARMv4.
|
|
unsigned getReturnOpcode() const {
|
|
if (isThumb())
|
|
return ARM::tBX_RET;
|
|
if (hasV4TOps())
|
|
return ARM::BX_RET;
|
|
return ARM::MOVPCLR;
|
|
}
|
|
|
|
/// Allow movt+movw for PIC global address calculation.
|
|
/// ELF does not have GOT relocations for movt+movw.
|
|
/// ROPI does not use GOT.
|
|
bool allowPositionIndependentMovt() const {
|
|
return isROPI() || !isTargetELF();
|
|
}
|
|
|
|
unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
|
|
|
|
unsigned
|
|
getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const {
|
|
if (CostKind == TargetTransformInfo::TCK_CodeSize)
|
|
return 1;
|
|
return MVEVectorCostFactor;
|
|
}
|
|
|
|
bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
|
|
unsigned PhysReg) const override;
|
|
unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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