28233408a2
When using Greedy Register Allocation, there are times where early-clobber values are ignored, and assigned the same register. This is illeagal behaviour for these intructions. To get around this, using Pseudo instructions for early-clobber registers gives them a definition and allows Greedy to assign them to a different register. This then meets the ARM Architecture Reference Manual and matches the defined behaviour. This patch takes the existing RISC-V patch and makes it target independent, then adds support for the ARM Architecture. Doing this will ensure early-clobber restraints are followed when using the ARM Architecture. Making the pass target independent will also open up possibility that support other architectures can be added in the future.
97 lines
3.4 KiB
C++
97 lines
3.4 KiB
C++
//===-- RISCV.h - Top-level interface for RISC-V ----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// RISC-V back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
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#define LLVM_LIB_TARGET_RISCV_RISCV_H
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class FunctionPass;
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class InstructionSelector;
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class PassRegistry;
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class RISCVRegisterBankInfo;
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class RISCVSubtarget;
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class RISCVTargetMachine;
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FunctionPass *createRISCVCodeGenPreparePass();
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void initializeRISCVCodeGenPreparePass(PassRegistry &);
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FunctionPass *createRISCVDeadRegisterDefinitionsPass();
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void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &);
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FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
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CodeGenOptLevel OptLevel);
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FunctionPass *createRISCVMakeCompressibleOptPass();
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void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
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FunctionPass *createRISCVGatherScatterLoweringPass();
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void initializeRISCVGatherScatterLoweringPass(PassRegistry &);
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FunctionPass *createRISCVFoldMasksPass();
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void initializeRISCVFoldMasksPass(PassRegistry &);
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FunctionPass *createRISCVOptWInstrsPass();
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void initializeRISCVOptWInstrsPass(PassRegistry &);
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FunctionPass *createRISCVMergeBaseOffsetOptPass();
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void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
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FunctionPass *createRISCVExpandPseudoPass();
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void initializeRISCVExpandPseudoPass(PassRegistry &);
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FunctionPass *createRISCVPreRAExpandPseudoPass();
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void initializeRISCVPreRAExpandPseudoPass(PassRegistry &);
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FunctionPass *createRISCVExpandAtomicPseudoPass();
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void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
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FunctionPass *createRISCVInsertVSETVLIPass();
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void initializeRISCVInsertVSETVLIPass(PassRegistry &);
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FunctionPass *createRISCVPostRAExpandPseudoPass();
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void initializeRISCVPostRAExpandPseudoPass(PassRegistry &);
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FunctionPass *createRISCVInsertReadWriteCSRPass();
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void initializeRISCVInsertReadWriteCSRPass(PassRegistry &);
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FunctionPass *createRISCVInsertWriteVXRMPass();
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void initializeRISCVInsertWriteVXRMPass(PassRegistry &);
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FunctionPass *createRISCVRedundantCopyEliminationPass();
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void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
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FunctionPass *createRISCVMoveMergePass();
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void initializeRISCVMoveMergePass(PassRegistry &);
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FunctionPass *createRISCVPushPopOptimizationPass();
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void initializeRISCVPushPopOptPass(PassRegistry &);
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InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
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RISCVSubtarget &,
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RISCVRegisterBankInfo &);
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void initializeRISCVDAGToDAGISelPass(PassRegistry &);
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FunctionPass *createRISCVPostLegalizerCombiner();
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void initializeRISCVPostLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createRISCVO0PreLegalizerCombiner();
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void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createRISCVPreLegalizerCombiner();
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void initializeRISCVPreLegalizerCombinerPass(PassRegistry &);
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} // namespace llvm
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#endif
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