3ac9fe69f7
This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register count to 16(x0-x16). * The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits. `RVE` can be combined with all current standard extensions. The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are: * Only 6 integer argument registers (rather than 8). * Only 2 callee-saved registers (rather than 12). * A Stack Alignment of 32bits (rather than 128bits). * ilp32e isn't compatible with D ISA extension. If `ilp32e` or `lp64` is used with an ISA that has any of the registers x16-x31 and f0-f31, then these registers are considered temporaries. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment\ to 4-bytes for types with length of 2*XLEN. FastCC is also supported on RVE, while GHC isn't since there is only one avaiable register. Differential Revision: https://reviews.llvm.org/D70401
55 lines
2.3 KiB
TableGen
55 lines
2.3 KiB
TableGen
//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the RISC-V architecture.
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//
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//===----------------------------------------------------------------------===//
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// The RISC-V calling convention is handled with custom code in
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// RISCVISelLowering.cpp (CC_RISCV).
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def CSR_ILP32E_LP64E : CalleeSavedRegs<(add X1, X8, X9)>;
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def CSR_ILP32_LP64
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: CalleeSavedRegs<(add CSR_ILP32E_LP64E, (sequence "X%u", 18, 27))>;
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def CSR_ILP32F_LP64F
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
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def CSR_ILP32D_LP64D
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
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// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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// Interrupt handler needs to save/restore all registers that are used,
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// both Caller and Callee saved registers.
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def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>;
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// Same as CSR_Interrupt, but including all 32-bit FP registers.
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def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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(sequence "F%u_F", 0, 31))>;
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// Same as CSR_Interrupt, but including all 64-bit FP registers.
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def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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(sequence "F%u_D", 0, 31))>;
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// Same as CSR_Interrupt, but excluding X16-X31.
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def CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt,
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(sequence "X%u", 16, 31))>;
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// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31.
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def CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt,
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(sequence "X%u", 16, 31))>;
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// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31.
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def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt,
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(sequence "X%u", 16, 31))>;
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