28233408a2
When using Greedy Register Allocation, there are times where early-clobber values are ignored, and assigned the same register. This is illeagal behaviour for these intructions. To get around this, using Pseudo instructions for early-clobber registers gives them a definition and allows Greedy to assign them to a different register. This then meets the ARM Architecture Reference Manual and matches the defined behaviour. This patch takes the existing RISC-V patch and makes it target independent, then adds support for the ARM Architecture. Doing this will ensure early-clobber restraints are followed when using the ARM Architecture. Making the pass target independent will also open up possibility that support other architectures can be added in the future.
351 lines
14 KiB
C++
351 lines
14 KiB
C++
//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISC-V implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
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#include "RISCV.h"
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#include "RISCVRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#define GET_INSTRINFO_HEADER
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#define GET_INSTRINFO_OPERAND_ENUM
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#include "RISCVGenInstrInfo.inc"
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#include "RISCVGenRegisterInfo.inc"
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namespace llvm {
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class RISCVSubtarget;
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static const MachineMemOperand::Flags MONontemporalBit0 =
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MachineMemOperand::MOTargetFlag1;
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static const MachineMemOperand::Flags MONontemporalBit1 =
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MachineMemOperand::MOTargetFlag2;
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namespace RISCVCC {
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enum CondCode {
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COND_EQ,
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COND_NE,
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COND_LT,
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COND_GE,
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COND_LTU,
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COND_GEU,
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COND_INVALID
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};
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CondCode getOppositeBranchCondition(CondCode);
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unsigned getBrCond(CondCode CC);
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} // end of namespace RISCVCC
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class RISCVInstrInfo : public RISCVGenInstrInfo {
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public:
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explicit RISCVInstrInfo(RISCVSubtarget &STI);
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MCInst getNop() const override;
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const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
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Register isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
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unsigned &MemBytes) const override;
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Register isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
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unsigned &MemBytes) const override;
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void copyPhysRegVector(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
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MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
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unsigned Opc, unsigned NF = 1) const;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool IsKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register DstReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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using TargetInstrInfo::foldMemoryOperandImpl;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt,
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int FrameIndex,
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LiveIntervals *LIS = nullptr,
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VirtRegMap *VRM = nullptr) const override;
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// Materializes the given integer Val into DstReg.
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void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, Register DstReg, uint64_t Val,
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MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
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bool DstRenamable = false, bool DstIsDead = false) const;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &dl,
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int *BytesAdded = nullptr) const override;
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void insertIndirectBranch(MachineBasicBlock &MBB,
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MachineBasicBlock &NewDestBB,
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MachineBasicBlock &RestoreBB, const DebugLoc &DL,
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int64_t BrOffset, RegScavenger *RS) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool optimizeCondBranch(MachineInstr &MI) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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bool analyzeSelect(const MachineInstr &MI,
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SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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unsigned &FalseOp, bool &Optimizable) const override;
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MachineInstr *optimizeSelect(MachineInstr &MI,
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SmallPtrSetImpl<MachineInstr *> &SeenMIs,
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bool) const override;
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bool isAsCheapAsAMove(const MachineInstr &MI) const override;
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std::optional<DestSourcePair>
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isCopyInstrImpl(const MachineInstr &MI) const override;
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
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const MachineInstr &AddrI,
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ExtAddrMode &AM) const override;
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MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
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const ExtAddrMode &AM) const override;
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bool getMemOperandsWithOffsetWidth(
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const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
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int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
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const TargetRegisterInfo *TRI) const override;
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bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
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int64_t Offset1, bool OffsetIsScalable1,
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ArrayRef<const MachineOperand *> BaseOps2,
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int64_t Offset2, bool OffsetIsScalable2,
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unsigned ClusterSize,
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unsigned NumBytes) const override;
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bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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const MachineOperand *&BaseOp,
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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// Return true if the function can safely be outlined from.
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bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
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bool OutlineFromLinkOnceODRs) const override;
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// Return true if MBB is safe to outline from, and return any target-specific
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// information in Flags.
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bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
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unsigned &Flags) const override;
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bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
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// Calculate target-specific information for a set of outlining candidates.
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std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
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std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
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// Return if/how a given MachineInstr should be outlined.
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virtual outliner::InstrType
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getOutliningTypeImpl(MachineBasicBlock::iterator &MBBI,
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unsigned Flags) const override;
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// Insert a custom frame for outlined functions.
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void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
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const outliner::OutlinedFunction &OF) const override;
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// Insert a call to an outlined function into a given basic block.
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MachineBasicBlock::iterator
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insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &It, MachineFunction &MF,
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outliner::Candidate &C) const override;
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std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
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Register Reg) const override;
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
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LiveIntervals *LIS) const override;
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// MIR printer helper function to annotate Operands with a comment.
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std::string
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createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
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unsigned OpIdx,
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const TargetRegisterInfo *TRI) const override;
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void getVLENFactoredAmount(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg,
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int64_t Amount, MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
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bool useMachineCombiner() const override { return true; }
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MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
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bool
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getMachineCombinerPatterns(MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern> &Patterns,
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bool DoRegPressureReduce) const override;
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void
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finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
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SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
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void genAlternativeCodeSequence(
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MachineInstr &Root, MachineCombinerPattern Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
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bool hasReassociableSibling(const MachineInstr &Inst,
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bool &Commuted) const override;
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bool isAssociativeAndCommutative(const MachineInstr &Inst,
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bool Invert) const override;
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std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
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ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
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getSerializableMachineMemOperandTargetFlags() const override;
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unsigned getUndefInitOpcode(unsigned RegClassID) const override {
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switch (RegClassID) {
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case RISCV::VRRegClassID:
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return RISCV::PseudoRVVInitUndefM1;
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case RISCV::VRM2RegClassID:
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return RISCV::PseudoRVVInitUndefM2;
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case RISCV::VRM4RegClassID:
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return RISCV::PseudoRVVInitUndefM4;
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case RISCV::VRM8RegClassID:
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return RISCV::PseudoRVVInitUndefM8;
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default:
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llvm_unreachable("Unexpected register class.");
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}
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}
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protected:
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const RISCVSubtarget &STI;
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private:
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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};
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namespace RISCV {
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// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
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bool isSEXT_W(const MachineInstr &MI);
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bool isZEXT_W(const MachineInstr &MI);
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bool isZEXT_B(const MachineInstr &MI);
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// Returns true if the given MI is an RVV instruction opcode for which we may
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// expect to see a FrameIndex operand.
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bool isRVVSpill(const MachineInstr &MI);
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std::optional<std::pair<unsigned, unsigned>>
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isRVVSpillForZvlsseg(unsigned Opcode);
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bool isFaultFirstLoad(const MachineInstr &MI);
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// Implemented in RISCVGenInstrInfo.inc
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
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// Return true if both input instructions have equal rounding mode. If at least
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// one of the instructions does not have rounding mode, false will be returned.
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bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
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// If \p Opcode is a .vx vector instruction, returns the lower number of bits
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// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
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// returns null.
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std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
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unsigned Log2SEW);
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// Returns the MC opcode of RVV pseudo instruction.
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unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
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// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
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static constexpr int64_t VLMaxSentinel = -1LL;
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// Mask assignments for floating-point
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static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
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static constexpr unsigned FPMASK_Negative_Normal = 0x002;
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static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
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static constexpr unsigned FPMASK_Negative_Zero = 0x008;
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static constexpr unsigned FPMASK_Positive_Zero = 0x010;
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static constexpr unsigned FPMASK_Positive_Subnormal = 0x020;
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static constexpr unsigned FPMASK_Positive_Normal = 0x040;
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static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
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static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
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static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
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} // namespace RISCV
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namespace RISCVVPseudosTable {
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struct PseudoInfo {
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uint16_t Pseudo;
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uint16_t BaseInstr;
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};
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#define GET_RISCVVPseudosTable_DECL
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#include "RISCVGenSearchableTables.inc"
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} // end namespace RISCVVPseudosTable
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} // end namespace llvm
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#endif
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