6cca23a3b9
This PR is to prevent creation of jump tables from switch. The reason is
that SPIR-V doesn't know how to lower jump tables, and a sequence of
commands that IRTranslator generates for switch via jump tables breaks
SPIR-V Backend code generation with complains to G_BRJT. The next
example is the shortest code to break SPIR-V Backend code generation in
this way:
```
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
target triple = "spir64-unknown-unknown"
define spir_func void @foo(i32 noundef %val) {
entry:
switch i32 %val, label %sw.epilog [
i32 0, label %sw.bb
i32 1, label %sw.bb2
i32 2, label %sw.bb3
i32 3, label %sw.bb4
]
sw.bb:
br label %sw.epilog
sw.bb2:
br label %sw.epilog
sw.bb3:
br label %sw.epilog
sw.bb4:
br label %sw.epilog
sw.epilog:
ret void
}
```
To resolve the issue we set a high lower limit for number of blocks in a
jump table via getMinimumJumpTableEntries() and prevent undesirable (or
rather unsupported at the moment) path of code generation.
54 lines
2.0 KiB
C++
54 lines
2.0 KiB
C++
//===-- SPIRVISelLowering.h - SPIR-V DAG Lowering Interface -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that SPIR-V uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
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#define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class SPIRVSubtarget;
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class SPIRVTargetLowering : public TargetLowering {
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public:
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explicit SPIRVTargetLowering(const TargetMachine &TM,
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const SPIRVSubtarget &STI)
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: TargetLowering(TM) {}
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// Stop IRTranslator breaking up FMA instrs to preserve types information.
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT) const override {
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return true;
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}
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// prevent creation of jump tables
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bool areJTsAllowed(const Function *) const override { return false; }
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// This is to prevent sexts of non-i64 vector indices which are generated
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// within general IRTranslator hence type generation for it is omitted.
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MVT getVectorIdxTy(const DataLayout &DL) const override {
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return MVT::getIntegerVT(32);
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}
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unsigned getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
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EVT VT) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
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