7b08b4360b
This new analysis returns a hierarchical view of the convergence regions in the given function. This will allow our passes to query which basic block belongs to which convergence region, and structurize the code in consequence. Definition ---------- A convergence region is a CFG with: - a single entry node. - one or multiple exit nodes (different from LLVM's regions). - one back-edge - zero or more subregions. Excluding sub-regions nodes, the nodes of a region can only reference a single convergence token. A subregion uses a different convergence token. Algorithm --------- This algorithm assumes all loops are in the Simplify form. Create an initial convergence region for the whole function. - the convergence token is the function entry token. - the entry is the function entrypoint. - Exits are all the basic blocks terminating with a return instruction. Take the function CFG, and process it in DAG order (ignoring back-edges). If a basic block is a loop header: - Create a new region. - The parent region is the parent's loop region if any, otherwise, the top level region. - The region blocks are all the blocks belonging to this loop. - For each loop exit: - visit the rest of the CFG in DAG order (ignore back-edges). - if the region's convergence token is found, add all the blocks dominated by the exit from which the token is reachable to the region. - continue the algorithm with the loop headers successors.
218 lines
7.5 KiB
C++
218 lines
7.5 KiB
C++
//===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about SPIR-V target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVTargetMachine.h"
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#include "SPIRV.h"
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#include "SPIRVCallLowering.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVLegalizerInfo.h"
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#include "SPIRVTargetObjectFile.h"
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#include "SPIRVTargetTransformInfo.h"
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#include "TargetInfo/SPIRVTargetInfo.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Pass.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Utils.h"
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#include <optional>
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using namespace llvm;
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget() {
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// Register the target.
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RegisterTargetMachine<SPIRVTargetMachine> X(getTheSPIRV32Target());
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RegisterTargetMachine<SPIRVTargetMachine> Y(getTheSPIRV64Target());
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RegisterTargetMachine<SPIRVTargetMachine> Z(getTheSPIRVLogicalTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeGlobalISel(PR);
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initializeSPIRVModuleAnalysisPass(PR);
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initializeSPIRVConvergenceRegionAnalysisWrapperPassPass(PR);
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}
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static std::string computeDataLayout(const Triple &TT) {
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const auto Arch = TT.getArch();
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// TODO: this probably needs to be revisited:
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// Logical SPIR-V has no pointer size, so any fixed pointer size would be
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// wrong. The choice to default to 32 or 64 is just motivated by another
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// memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
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// mean anything.
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if (Arch == Triple::spirv32)
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return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
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"v96:128-v192:256-v256:256-v512:512-v1024:1024";
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return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
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"v96:128-v192:256-v256:256-v512:512-v1024:1024";
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}
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static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
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if (!RM)
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return Reloc::PIC_;
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return *RM;
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}
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// Pin SPIRVTargetObjectFile's vtables to this file.
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SPIRVTargetObjectFile::~SPIRVTargetObjectFile() {}
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SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(std::make_unique<SPIRVTargetObjectFile>()),
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Subtarget(TT, CPU.str(), FS.str(), *this) {
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initAsmInfo();
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setGlobalISel(true);
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setFastISel(false);
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setO0WantsFastISel(false);
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setRequiresStructuredCFG(false);
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}
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namespace {
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// SPIR-V Code Generator Pass Configuration Options.
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class SPIRVPassConfig : public TargetPassConfig {
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public:
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SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM), TM(TM) {}
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SPIRVTargetMachine &getSPIRVTargetMachine() const {
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return getTM<SPIRVTargetMachine>();
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}
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void addIRPasses() override;
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void addISelPrepare() override;
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bool addIRTranslator() override;
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void addPreLegalizeMachineIR() override;
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bool addLegalizeMachineIR() override;
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bool addRegBankSelect() override;
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bool addGlobalInstructionSelect() override;
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FunctionPass *createTargetRegisterAllocator(bool) override;
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void addFastRegAlloc() override {}
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void addOptimizedRegAlloc() override {}
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void addPostRegAlloc() override;
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private:
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const SPIRVTargetMachine &TM;
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};
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} // namespace
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// We do not use physical registers, and maintain virtual registers throughout
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// the entire pipeline, so return nullptr to disable register allocation.
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FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
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return nullptr;
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}
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// Disable passes that break from assuming no virtual registers exist.
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void SPIRVPassConfig::addPostRegAlloc() {
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// Do not work with vregs instead of physical regs.
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disablePass(&MachineCopyPropagationID);
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disablePass(&PostRAMachineSinkingID);
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disablePass(&PostRASchedulerID);
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disablePass(&FuncletLayoutID);
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disablePass(&StackMapLivenessID);
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disablePass(&PatchableFunctionID);
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disablePass(&ShrinkWrapID);
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disablePass(&LiveDebugValuesID);
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disablePass(&MachineLateInstrsCleanupID);
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// Do not work with OpPhi.
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disablePass(&BranchFolderPassID);
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disablePass(&MachineBlockPlacementID);
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TargetPassConfig::addPostRegAlloc();
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}
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TargetTransformInfo
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SPIRVTargetMachine::getTargetTransformInfo(const Function &F) const {
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return TargetTransformInfo(SPIRVTTIImpl(this, F));
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}
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TargetPassConfig *SPIRVTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new SPIRVPassConfig(*this, PM);
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}
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void SPIRVPassConfig::addIRPasses() {
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if (TM.getSubtargetImpl()->isVulkanEnv()) {
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// Once legalized, we need to structurize the CFG to follow the spec.
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// This is done through the following 8 steps.
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// TODO(#75801): add the remaining steps.
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// 1. Simplify loop for subsequent transformations. After this steps, loops
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// have the following properties:
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// - loops have a single entry edge (pre-header to loop header).
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// - all loop exits are dominated by the loop pre-header.
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// - loops have a single back-edge.
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addPass(createLoopSimplifyPass());
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}
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TargetPassConfig::addIRPasses();
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addPass(createSPIRVRegularizerPass());
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addPass(createSPIRVPrepareFunctionsPass(TM));
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addPass(createSPIRVStripConvergenceIntrinsicsPass());
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}
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void SPIRVPassConfig::addISelPrepare() {
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addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
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TargetPassConfig::addISelPrepare();
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}
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bool SPIRVPassConfig::addIRTranslator() {
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addPass(new IRTranslator(getOptLevel()));
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return false;
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}
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void SPIRVPassConfig::addPreLegalizeMachineIR() {
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addPass(createSPIRVPreLegalizerPass());
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}
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// Use the default legalizer.
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bool SPIRVPassConfig::addLegalizeMachineIR() {
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addPass(new Legalizer());
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return false;
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}
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// Do not add the RegBankSelect pass, as we only ever need virtual registers.
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bool SPIRVPassConfig::addRegBankSelect() {
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disablePass(&RegBankSelect::ID);
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return false;
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}
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namespace {
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// A custom subclass of InstructionSelect, which is mostly the same except from
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// not requiring RegBankSelect to occur previously.
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class SPIRVInstructionSelect : public InstructionSelect {
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// We don't use register banks, so unset the requirement for them
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MachineFunctionProperties getRequiredProperties() const override {
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return InstructionSelect::getRequiredProperties().reset(
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MachineFunctionProperties::Property::RegBankSelected);
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}
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};
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} // namespace
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// Add the custom SPIRVInstructionSelect from above.
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bool SPIRVPassConfig::addGlobalInstructionSelect() {
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addPass(new SPIRVInstructionSelect());
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return false;
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}
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