984dc4b9cd
Move WebAssemblyUtilities from Utils to the CodeGen library. It primarily deals in MIR layer types, so it really lives in the CodeGen library. Move a variety of other things around to try create better separation. See issue #64166 for more info on layering. Move llvm/include/CodeGen/WasmAddressSpaces.h back to llvm/lib/Target/WebAssembly/Utils. Differential Revision: https://reviews.llvm.org/D156472
399 lines
15 KiB
C++
399 lines
15 KiB
C++
//===-- WebAssemblyCFGSort.cpp - CFG Sorting ------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements a CFG sorting pass.
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///
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/// This pass reorders the blocks in a function to put them into topological
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/// order, ignoring loop backedges, and without any loop or exception being
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/// interrupted by a block not dominated by the its header, with special care
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/// to keep the order as similar as possible to the original order.
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///
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////===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyExceptionInfo.h"
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#include "WebAssemblySortRegion.h"
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#include "WebAssemblySubtarget.h"
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#include "WebAssemblyUtilities.h"
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#include "llvm/ADT/PriorityQueue.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/WasmEHFuncInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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using WebAssembly::SortRegion;
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using WebAssembly::SortRegionInfo;
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#define DEBUG_TYPE "wasm-cfg-sort"
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// Option to disable EH pad first sorting. Only for testing unwind destination
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// mismatches in CFGStackify.
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static cl::opt<bool> WasmDisableEHPadSort(
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"wasm-disable-ehpad-sort", cl::ReallyHidden,
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cl::desc(
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"WebAssembly: Disable EH pad-first sort order. Testing purpose only."),
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cl::init(false));
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namespace {
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class WebAssemblyCFGSort final : public MachineFunctionPass {
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StringRef getPassName() const override { return "WebAssembly CFG Sort"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<WebAssemblyExceptionInfo>();
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AU.addPreserved<WebAssemblyExceptionInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyCFGSort() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyCFGSort::ID = 0;
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INITIALIZE_PASS(WebAssemblyCFGSort, DEBUG_TYPE,
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"Reorders blocks in topological order", false, false)
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FunctionPass *llvm::createWebAssemblyCFGSort() {
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return new WebAssemblyCFGSort();
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}
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static void maybeUpdateTerminator(MachineBasicBlock *MBB) {
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#ifndef NDEBUG
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bool AnyBarrier = false;
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#endif
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bool AllAnalyzable = true;
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for (const MachineInstr &Term : MBB->terminators()) {
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#ifndef NDEBUG
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AnyBarrier |= Term.isBarrier();
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#endif
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AllAnalyzable &= Term.isBranch() && !Term.isIndirectBranch();
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}
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assert((AnyBarrier || AllAnalyzable) &&
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"analyzeBranch needs to analyze any block with a fallthrough");
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// Find the layout successor from the original block order.
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MachineFunction *MF = MBB->getParent();
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MachineBasicBlock *OriginalSuccessor =
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unsigned(MBB->getNumber() + 1) < MF->getNumBlockIDs()
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? MF->getBlockNumbered(MBB->getNumber() + 1)
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: nullptr;
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if (AllAnalyzable)
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MBB->updateTerminator(OriginalSuccessor);
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}
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namespace {
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// EH pads are selected first regardless of the block comparison order.
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// When only one of the BBs is an EH pad, we give a higher priority to it, to
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// prevent common mismatches between possibly throwing calls and ehpads they
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// unwind to, as in the example below:
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//
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// bb0:
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// call @foo // If this throws, unwind to bb2
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// bb1:
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// call @bar // If this throws, unwind to bb3
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// bb2 (ehpad):
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// handler_bb2
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// bb3 (ehpad):
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// handler_bb3
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// continuing code
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//
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// Because this pass tries to preserve the original BB order, this order will
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// not change. But this will result in this try-catch structure in CFGStackify,
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// resulting in a mismatch:
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// try
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// try
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// call @foo
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// call @bar // This should unwind to bb3, not bb2!
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// catch
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// handler_bb2
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// end
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// catch
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// handler_bb3
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// end
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// continuing code
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//
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// If we give a higher priority to an EH pad whenever it is ready in this
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// example, when both bb1 and bb2 are ready, we would pick up bb2 first.
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/// Sort blocks by their number.
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struct CompareBlockNumbers {
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bool operator()(const MachineBasicBlock *A,
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const MachineBasicBlock *B) const {
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if (!WasmDisableEHPadSort) {
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if (A->isEHPad() && !B->isEHPad())
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return false;
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if (!A->isEHPad() && B->isEHPad())
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return true;
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}
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return A->getNumber() > B->getNumber();
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}
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};
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/// Sort blocks by their number in the opposite order..
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struct CompareBlockNumbersBackwards {
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bool operator()(const MachineBasicBlock *A,
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const MachineBasicBlock *B) const {
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if (!WasmDisableEHPadSort) {
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if (A->isEHPad() && !B->isEHPad())
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return false;
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if (!A->isEHPad() && B->isEHPad())
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return true;
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}
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return A->getNumber() < B->getNumber();
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}
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};
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/// Bookkeeping for a region to help ensure that we don't mix blocks not
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/// dominated by the its header among its blocks.
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struct Entry {
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const SortRegion *TheRegion;
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unsigned NumBlocksLeft;
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/// List of blocks not dominated by Loop's header that are deferred until
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/// after all of Loop's blocks have been seen.
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std::vector<MachineBasicBlock *> Deferred;
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explicit Entry(const SortRegion *R)
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: TheRegion(R), NumBlocksLeft(R->getNumBlocks()) {}
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};
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} // end anonymous namespace
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/// Sort the blocks, taking special care to make sure that regions are not
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/// interrupted by blocks not dominated by their header.
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/// TODO: There are many opportunities for improving the heuristics here.
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/// Explore them.
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static void sortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI,
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const WebAssemblyExceptionInfo &WEI,
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const MachineDominatorTree &MDT) {
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// Remember original layout ordering, so we can update terminators after
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// reordering to point to the original layout successor.
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MF.RenumberBlocks();
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// Prepare for a topological sort: Record the number of predecessors each
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// block has, ignoring loop backedges.
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SmallVector<unsigned, 16> NumPredsLeft(MF.getNumBlockIDs(), 0);
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for (MachineBasicBlock &MBB : MF) {
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unsigned N = MBB.pred_size();
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if (MachineLoop *L = MLI.getLoopFor(&MBB))
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if (L->getHeader() == &MBB)
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for (const MachineBasicBlock *Pred : MBB.predecessors())
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if (L->contains(Pred))
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--N;
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NumPredsLeft[MBB.getNumber()] = N;
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}
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// Topological sort the CFG, with additional constraints:
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// - Between a region header and the last block in the region, there can be
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// no blocks not dominated by its header.
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// - It's desirable to preserve the original block order when possible.
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// We use two ready lists; Preferred and Ready. Preferred has recently
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// processed successors, to help preserve block sequences from the original
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// order. Ready has the remaining ready blocks. EH blocks are picked first
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// from both queues.
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PriorityQueue<MachineBasicBlock *, std::vector<MachineBasicBlock *>,
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CompareBlockNumbers>
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Preferred;
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PriorityQueue<MachineBasicBlock *, std::vector<MachineBasicBlock *>,
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CompareBlockNumbersBackwards>
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Ready;
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const auto *EHInfo = MF.getWasmEHFuncInfo();
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SortRegionInfo SRI(MLI, WEI);
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SmallVector<Entry, 4> Entries;
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for (MachineBasicBlock *MBB = &MF.front();;) {
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const SortRegion *R = SRI.getRegionFor(MBB);
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if (R) {
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// If MBB is a region header, add it to the active region list. We can't
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// put any blocks that it doesn't dominate until we see the end of the
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// region.
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if (R->getHeader() == MBB)
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Entries.push_back(Entry(R));
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// For each active region the block is in, decrement the count. If MBB is
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// the last block in an active region, take it off the list and pick up
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// any blocks deferred because the header didn't dominate them.
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for (Entry &E : Entries)
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if (E.TheRegion->contains(MBB) && --E.NumBlocksLeft == 0)
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for (auto *DeferredBlock : E.Deferred)
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Ready.push(DeferredBlock);
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while (!Entries.empty() && Entries.back().NumBlocksLeft == 0)
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Entries.pop_back();
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}
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// The main topological sort logic.
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for (MachineBasicBlock *Succ : MBB->successors()) {
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// Ignore backedges.
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if (MachineLoop *SuccL = MLI.getLoopFor(Succ))
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if (SuccL->getHeader() == Succ && SuccL->contains(MBB))
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continue;
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// Decrement the predecessor count. If it's now zero, it's ready.
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if (--NumPredsLeft[Succ->getNumber()] == 0) {
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// When we are in a SortRegion, we allow sorting of not only BBs that
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// belong to the current (innermost) region but also BBs that are
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// dominated by the current region header. But we should not do this for
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// exceptions because there can be cases in which, for example:
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// EHPad A's unwind destination (where the exception lands when it is
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// not caught by EHPad A) is EHPad B, so EHPad B does not belong to the
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// exception dominated by EHPad A. But EHPad B is dominated by EHPad A,
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// so EHPad B can be sorted within EHPad A's exception. This is
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// incorrect because we may end up delegating/rethrowing to an inner
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// scope in CFGStackify. So here we make sure those unwind destinations
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// are deferred until their unwind source's exception is sorted.
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if (EHInfo && EHInfo->hasUnwindSrcs(Succ)) {
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SmallPtrSet<MachineBasicBlock *, 4> UnwindSrcs =
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EHInfo->getUnwindSrcs(Succ);
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bool IsDeferred = false;
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for (Entry &E : Entries) {
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if (UnwindSrcs.count(E.TheRegion->getHeader())) {
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E.Deferred.push_back(Succ);
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IsDeferred = true;
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break;
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}
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}
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if (IsDeferred)
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continue;
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}
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Preferred.push(Succ);
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}
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}
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// Determine the block to follow MBB. First try to find a preferred block,
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// to preserve the original block order when possible.
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MachineBasicBlock *Next = nullptr;
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while (!Preferred.empty()) {
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Next = Preferred.top();
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Preferred.pop();
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// If X isn't dominated by the top active region header, defer it until
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// that region is done.
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if (!Entries.empty() &&
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!MDT.dominates(Entries.back().TheRegion->getHeader(), Next)) {
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Entries.back().Deferred.push_back(Next);
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Next = nullptr;
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continue;
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}
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// If Next was originally ordered before MBB, and it isn't because it was
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// loop-rotated above the header, it's not preferred.
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if (Next->getNumber() < MBB->getNumber() &&
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(WasmDisableEHPadSort || !Next->isEHPad()) &&
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(!R || !R->contains(Next) ||
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R->getHeader()->getNumber() < Next->getNumber())) {
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Ready.push(Next);
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Next = nullptr;
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continue;
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}
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break;
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}
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// If we didn't find a suitable block in the Preferred list, check the
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// general Ready list.
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if (!Next) {
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// If there are no more blocks to process, we're done.
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if (Ready.empty()) {
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maybeUpdateTerminator(MBB);
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break;
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}
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for (;;) {
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Next = Ready.top();
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Ready.pop();
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// If Next isn't dominated by the top active region header, defer it
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// until that region is done.
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if (!Entries.empty() &&
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!MDT.dominates(Entries.back().TheRegion->getHeader(), Next)) {
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Entries.back().Deferred.push_back(Next);
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continue;
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}
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break;
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}
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}
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// Move the next block into place and iterate.
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Next->moveAfter(MBB);
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maybeUpdateTerminator(MBB);
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MBB = Next;
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}
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assert(Entries.empty() && "Active sort region list not finished");
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MF.RenumberBlocks();
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#ifndef NDEBUG
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SmallSetVector<const SortRegion *, 8> OnStack;
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// Insert a sentinel representing the degenerate loop that starts at the
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// function entry block and includes the entire function as a "loop" that
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// executes once.
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OnStack.insert(nullptr);
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for (auto &MBB : MF) {
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assert(MBB.getNumber() >= 0 && "Renumbered blocks should be non-negative.");
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const SortRegion *Region = SRI.getRegionFor(&MBB);
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if (Region && &MBB == Region->getHeader()) {
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// Region header.
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if (Region->isLoop()) {
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// Loop header. The loop predecessor should be sorted above, and the
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// other predecessors should be backedges below.
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for (auto *Pred : MBB.predecessors())
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assert(
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(Pred->getNumber() < MBB.getNumber() || Region->contains(Pred)) &&
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"Loop header predecessors must be loop predecessors or "
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"backedges");
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} else {
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// Exception header. All predecessors should be sorted above.
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for (auto *Pred : MBB.predecessors())
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assert(Pred->getNumber() < MBB.getNumber() &&
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"Non-loop-header predecessors should be topologically sorted");
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}
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assert(OnStack.insert(Region) &&
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"Regions should be declared at most once.");
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} else {
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// Not a region header. All predecessors should be sorted above.
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for (auto *Pred : MBB.predecessors())
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assert(Pred->getNumber() < MBB.getNumber() &&
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"Non-loop-header predecessors should be topologically sorted");
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assert(OnStack.count(SRI.getRegionFor(&MBB)) &&
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"Blocks must be nested in their regions");
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}
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while (OnStack.size() > 1 && &MBB == SRI.getBottom(OnStack.back()))
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OnStack.pop_back();
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}
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assert(OnStack.pop_back_val() == nullptr &&
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"The function entry block shouldn't actually be a region header");
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assert(OnStack.empty() &&
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"Control flow stack pushes and pops should be balanced.");
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#endif
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}
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bool WebAssemblyCFGSort::runOnMachineFunction(MachineFunction &MF) {
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LLVM_DEBUG(dbgs() << "********** CFG Sorting **********\n"
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"********** Function: "
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<< MF.getName() << '\n');
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const auto &MLI = getAnalysis<MachineLoopInfo>();
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const auto &WEI = getAnalysis<WebAssemblyExceptionInfo>();
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auto &MDT = getAnalysis<MachineDominatorTree>();
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// Liveness is not tracked for VALUE_STACK physreg.
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MF.getRegInfo().invalidateLiveness();
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// Sort the blocks, with contiguous sort regions.
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sortBlocks(MF, MLI, WEI, MDT);
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return true;
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}
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