bef25ae297
Fixes #81136 - we might be loading from a constant pool entry wider than the destination register bitwidth, affecting the vextload scale calculation. ConvertToBroadcastAVX512 doesn't yet set an explicit bitwidth (it will default to the constant pool bitwidth) due to difficulties in looking up the original register width through the fold tables, but as we only use rebuildSplatCst this shouldn't cause any miscompilations, although it might prevent folding to broadcast if only the lower bits match a splatable pattern.
689 lines
27 KiB
C++
689 lines
27 KiB
C++
//===-- X86FixupVectorConstants.cpp - optimize constant generation -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file examines all full size vector constant pool loads and attempts to
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// replace them with smaller constant pool entries, including:
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// * Converting AVX512 memory-fold instructions to their broadcast-fold form.
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// * Using vzload scalar loads.
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// * Broadcasting of full width loads.
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// * Sign/Zero extension of full width loads.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrFoldTables.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-fixup-vector-constants"
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STATISTIC(NumInstChanges, "Number of instructions changes");
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namespace {
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class X86FixupVectorConstantsPass : public MachineFunctionPass {
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public:
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static char ID;
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X86FixupVectorConstantsPass() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "X86 Fixup Vector Constants";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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bool processInstruction(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineInstr &MI);
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// This pass runs after regalloc and doesn't support VReg operands.
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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const X86InstrInfo *TII = nullptr;
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const X86Subtarget *ST = nullptr;
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const MCSchedModel *SM = nullptr;
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};
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} // end anonymous namespace
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char X86FixupVectorConstantsPass::ID = 0;
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INITIALIZE_PASS(X86FixupVectorConstantsPass, DEBUG_TYPE, DEBUG_TYPE, false, false)
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FunctionPass *llvm::createX86FixupVectorConstants() {
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return new X86FixupVectorConstantsPass();
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}
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// Attempt to extract the full width of bits data from the constant.
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static std::optional<APInt> extractConstantBits(const Constant *C) {
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unsigned NumBits = C->getType()->getPrimitiveSizeInBits();
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if (isa<UndefValue>(C))
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return APInt::getZero(NumBits);
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if (auto *CInt = dyn_cast<ConstantInt>(C))
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return CInt->getValue();
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if (auto *CFP = dyn_cast<ConstantFP>(C))
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return CFP->getValue().bitcastToAPInt();
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if (auto *CV = dyn_cast<ConstantVector>(C)) {
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if (auto *CVSplat = CV->getSplatValue(/*AllowUndefs*/ true)) {
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if (std::optional<APInt> Bits = extractConstantBits(CVSplat)) {
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assert((NumBits % Bits->getBitWidth()) == 0 && "Illegal splat");
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return APInt::getSplat(NumBits, *Bits);
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}
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}
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APInt Bits = APInt::getZero(NumBits);
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for (unsigned I = 0, E = CV->getNumOperands(); I != E; ++I) {
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Constant *Elt = CV->getOperand(I);
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std::optional<APInt> SubBits = extractConstantBits(Elt);
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if (!SubBits)
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return std::nullopt;
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assert(NumBits == (E * SubBits->getBitWidth()) &&
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"Illegal vector element size");
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Bits.insertBits(*SubBits, I * SubBits->getBitWidth());
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}
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return Bits;
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}
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if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
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bool IsInteger = CDS->getElementType()->isIntegerTy();
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bool IsFloat = CDS->getElementType()->isHalfTy() ||
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CDS->getElementType()->isBFloatTy() ||
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CDS->getElementType()->isFloatTy() ||
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CDS->getElementType()->isDoubleTy();
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if (IsInteger || IsFloat) {
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APInt Bits = APInt::getZero(NumBits);
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unsigned EltBits = CDS->getElementType()->getPrimitiveSizeInBits();
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for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
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if (IsInteger)
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Bits.insertBits(CDS->getElementAsAPInt(I), I * EltBits);
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else
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Bits.insertBits(CDS->getElementAsAPFloat(I).bitcastToAPInt(),
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I * EltBits);
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}
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return Bits;
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}
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}
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return std::nullopt;
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}
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static std::optional<APInt> extractConstantBits(const Constant *C,
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unsigned NumBits) {
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if (std::optional<APInt> Bits = extractConstantBits(C))
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return Bits->zextOrTrunc(NumBits);
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return std::nullopt;
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}
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// Attempt to compute the splat width of bits data by normalizing the splat to
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// remove undefs.
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static std::optional<APInt> getSplatableConstant(const Constant *C,
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unsigned SplatBitWidth) {
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const Type *Ty = C->getType();
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assert((Ty->getPrimitiveSizeInBits() % SplatBitWidth) == 0 &&
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"Illegal splat width");
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if (std::optional<APInt> Bits = extractConstantBits(C))
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if (Bits->isSplat(SplatBitWidth))
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return Bits->trunc(SplatBitWidth);
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// Detect general splats with undefs.
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// TODO: Do we need to handle NumEltsBits > SplatBitWidth splitting?
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if (auto *CV = dyn_cast<ConstantVector>(C)) {
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unsigned NumOps = CV->getNumOperands();
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unsigned NumEltsBits = Ty->getScalarSizeInBits();
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unsigned NumScaleOps = SplatBitWidth / NumEltsBits;
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if ((SplatBitWidth % NumEltsBits) == 0) {
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// Collect the elements and ensure that within the repeated splat sequence
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// they either match or are undef.
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SmallVector<Constant *, 16> Sequence(NumScaleOps, nullptr);
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for (unsigned Idx = 0; Idx != NumOps; ++Idx) {
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if (Constant *Elt = CV->getAggregateElement(Idx)) {
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if (isa<UndefValue>(Elt))
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continue;
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unsigned SplatIdx = Idx % NumScaleOps;
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if (!Sequence[SplatIdx] || Sequence[SplatIdx] == Elt) {
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Sequence[SplatIdx] = Elt;
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continue;
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}
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}
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return std::nullopt;
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}
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// Extract the constant bits forming the splat and insert into the bits
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// data, leave undef as zero.
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APInt SplatBits = APInt::getZero(SplatBitWidth);
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for (unsigned I = 0; I != NumScaleOps; ++I) {
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if (!Sequence[I])
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continue;
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if (std::optional<APInt> Bits = extractConstantBits(Sequence[I])) {
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SplatBits.insertBits(*Bits, I * Bits->getBitWidth());
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continue;
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}
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return std::nullopt;
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}
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return SplatBits;
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}
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}
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return std::nullopt;
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}
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// Split raw bits into a constant vector of elements of a specific bit width.
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// NOTE: We don't always bother converting to scalars if the vector length is 1.
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static Constant *rebuildConstant(LLVMContext &Ctx, Type *SclTy,
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const APInt &Bits, unsigned NumSclBits) {
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unsigned BitWidth = Bits.getBitWidth();
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if (NumSclBits == 8) {
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SmallVector<uint8_t> RawBits;
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for (unsigned I = 0; I != BitWidth; I += 8)
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RawBits.push_back(Bits.extractBits(8, I).getZExtValue());
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return ConstantDataVector::get(Ctx, RawBits);
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}
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if (NumSclBits == 16) {
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SmallVector<uint16_t> RawBits;
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for (unsigned I = 0; I != BitWidth; I += 16)
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RawBits.push_back(Bits.extractBits(16, I).getZExtValue());
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if (SclTy->is16bitFPTy())
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return ConstantDataVector::getFP(SclTy, RawBits);
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return ConstantDataVector::get(Ctx, RawBits);
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}
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if (NumSclBits == 32) {
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SmallVector<uint32_t> RawBits;
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for (unsigned I = 0; I != BitWidth; I += 32)
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RawBits.push_back(Bits.extractBits(32, I).getZExtValue());
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if (SclTy->isFloatTy())
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return ConstantDataVector::getFP(SclTy, RawBits);
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return ConstantDataVector::get(Ctx, RawBits);
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}
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assert(NumSclBits == 64 && "Unhandled vector element width");
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SmallVector<uint64_t> RawBits;
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for (unsigned I = 0; I != BitWidth; I += 64)
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RawBits.push_back(Bits.extractBits(64, I).getZExtValue());
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if (SclTy->isDoubleTy())
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return ConstantDataVector::getFP(SclTy, RawBits);
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return ConstantDataVector::get(Ctx, RawBits);
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}
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// Attempt to rebuild a normalized splat vector constant of the requested splat
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// width, built up of potentially smaller scalar values.
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static Constant *rebuildSplatCst(const Constant *C, unsigned /*NumBits*/,
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unsigned /*NumElts*/, unsigned SplatBitWidth) {
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// TODO: Truncate to NumBits once ConvertToBroadcastAVX512 support this.
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std::optional<APInt> Splat = getSplatableConstant(C, SplatBitWidth);
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if (!Splat)
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return nullptr;
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// Determine scalar size to use for the constant splat vector, clamping as we
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// might have found a splat smaller than the original constant data.
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Type *SclTy = C->getType()->getScalarType();
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unsigned NumSclBits = SclTy->getPrimitiveSizeInBits();
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NumSclBits = std::min<unsigned>(NumSclBits, SplatBitWidth);
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// Fallback to i64 / double.
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NumSclBits = (NumSclBits == 8 || NumSclBits == 16 || NumSclBits == 32)
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? NumSclBits
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: 64;
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// Extract per-element bits.
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return rebuildConstant(C->getContext(), SclTy, *Splat, NumSclBits);
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}
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static Constant *rebuildZeroUpperCst(const Constant *C, unsigned NumBits,
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unsigned /*NumElts*/,
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unsigned ScalarBitWidth) {
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Type *SclTy = C->getType()->getScalarType();
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unsigned NumSclBits = SclTy->getPrimitiveSizeInBits();
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LLVMContext &Ctx = C->getContext();
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if (NumBits > ScalarBitWidth) {
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// Determine if the upper bits are all zero.
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if (std::optional<APInt> Bits = extractConstantBits(C, NumBits)) {
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if (Bits->countLeadingZeros() >= (NumBits - ScalarBitWidth)) {
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// If the original constant was made of smaller elements, try to retain
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// those types.
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if (ScalarBitWidth > NumSclBits && (ScalarBitWidth % NumSclBits) == 0)
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return rebuildConstant(Ctx, SclTy, *Bits, NumSclBits);
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// Fallback to raw integer bits.
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APInt RawBits = Bits->zextOrTrunc(ScalarBitWidth);
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return ConstantInt::get(Ctx, RawBits);
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}
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}
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}
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return nullptr;
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}
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static Constant *rebuildExtCst(const Constant *C, bool IsSExt,
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unsigned NumBits, unsigned NumElts,
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unsigned SrcEltBitWidth) {
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unsigned DstEltBitWidth = NumBits / NumElts;
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assert((NumBits % NumElts) == 0 && (NumBits % SrcEltBitWidth) == 0 &&
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(DstEltBitWidth % SrcEltBitWidth) == 0 &&
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(DstEltBitWidth > SrcEltBitWidth) && "Illegal extension width");
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if (std::optional<APInt> Bits = extractConstantBits(C, NumBits)) {
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assert((Bits->getBitWidth() / DstEltBitWidth) == NumElts &&
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(Bits->getBitWidth() % DstEltBitWidth) == 0 &&
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"Unexpected constant extension");
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// Ensure every vector element can be represented by the src bitwidth.
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APInt TruncBits = APInt::getZero(NumElts * SrcEltBitWidth);
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for (unsigned I = 0; I != NumElts; ++I) {
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APInt Elt = Bits->extractBits(DstEltBitWidth, I * DstEltBitWidth);
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if ((IsSExt && Elt.getSignificantBits() > SrcEltBitWidth) ||
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(!IsSExt && Elt.getActiveBits() > SrcEltBitWidth))
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return nullptr;
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TruncBits.insertBits(Elt.trunc(SrcEltBitWidth), I * SrcEltBitWidth);
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}
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Type *Ty = C->getType();
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return rebuildConstant(Ty->getContext(), Ty->getScalarType(), TruncBits,
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SrcEltBitWidth);
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}
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return nullptr;
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}
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static Constant *rebuildSExtCst(const Constant *C, unsigned NumBits,
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unsigned NumElts, unsigned SrcEltBitWidth) {
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return rebuildExtCst(C, true, NumBits, NumElts, SrcEltBitWidth);
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}
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static Constant *rebuildZExtCst(const Constant *C, unsigned NumBits,
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unsigned NumElts, unsigned SrcEltBitWidth) {
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return rebuildExtCst(C, false, NumBits, NumElts, SrcEltBitWidth);
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}
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bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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MachineConstantPool *CP = MI.getParent()->getParent()->getConstantPool();
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bool HasSSE41 = ST->hasSSE41();
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bool HasAVX2 = ST->hasAVX2();
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bool HasDQI = ST->hasDQI();
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bool HasBWI = ST->hasBWI();
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bool HasVLX = ST->hasVLX();
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struct FixupEntry {
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int Op;
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int NumCstElts;
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int MemBitWidth;
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std::function<Constant *(const Constant *, unsigned, unsigned, unsigned)>
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RebuildConstant;
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};
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auto FixupConstant = [&](ArrayRef<FixupEntry> Fixups, unsigned RegBitWidth,
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unsigned OperandNo) {
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#ifdef EXPENSIVE_CHECKS
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assert(llvm::is_sorted(Fixups,
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[](const FixupEntry &A, const FixupEntry &B) {
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return (A.NumCstElts * A.MemBitWidth) <
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(B.NumCstElts * B.MemBitWidth);
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}) &&
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"Constant fixup table not sorted in ascending constant size");
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#endif
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assert(MI.getNumOperands() >= (OperandNo + X86::AddrNumOperands) &&
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"Unexpected number of operands!");
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if (auto *C = X86::getConstantFromPool(MI, OperandNo)) {
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RegBitWidth =
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RegBitWidth ? RegBitWidth : C->getType()->getPrimitiveSizeInBits();
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for (const FixupEntry &Fixup : Fixups) {
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if (Fixup.Op) {
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// Construct a suitable constant and adjust the MI to use the new
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// constant pool entry.
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if (Constant *NewCst = Fixup.RebuildConstant(
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C, RegBitWidth, Fixup.NumCstElts, Fixup.MemBitWidth)) {
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unsigned NewCPI =
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CP->getConstantPoolIndex(NewCst, Align(Fixup.MemBitWidth / 8));
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MI.setDesc(TII->get(Fixup.Op));
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MI.getOperand(OperandNo + X86::AddrDisp).setIndex(NewCPI);
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return true;
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}
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}
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}
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}
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return false;
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};
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// Attempt to detect a suitable vzload/broadcast/vextload from increasing
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// constant bitwidths. Prefer vzload/broadcast/vextload for same bitwidth:
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// - vzload shouldn't ever need a shuffle port to zero the upper elements and
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// the fp/int domain versions are equally available so we don't introduce a
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// domain crossing penalty.
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// - broadcast sometimes need a shuffle port (especially for 8/16-bit
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// variants), AVX1 only has fp domain broadcasts but AVX2+ have good fp/int
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// domain equivalents.
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// - vextload always needs a shuffle port and is only ever int domain.
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switch (Opc) {
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/* FP Loads */
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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case X86::MOVUPDrm:
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case X86::MOVUPSrm:
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// TODO: SSE3 MOVDDUP Handling
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return FixupConstant({{X86::MOVSSrm, 1, 32, rebuildZeroUpperCst},
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{X86::MOVSDrm, 1, 64, rebuildZeroUpperCst}},
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128, 1);
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case X86::VMOVAPDrm:
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case X86::VMOVAPSrm:
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case X86::VMOVUPDrm:
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case X86::VMOVUPSrm:
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return FixupConstant({{X86::VMOVSSrm, 1, 32, rebuildZeroUpperCst},
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{X86::VBROADCASTSSrm, 1, 32, rebuildSplatCst},
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{X86::VMOVSDrm, 1, 64, rebuildZeroUpperCst},
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{X86::VMOVDDUPrm, 1, 64, rebuildSplatCst}},
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128, 1);
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case X86::VMOVAPDYrm:
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case X86::VMOVAPSYrm:
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case X86::VMOVUPDYrm:
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case X86::VMOVUPSYrm:
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return FixupConstant({{X86::VBROADCASTSSYrm, 1, 32, rebuildSplatCst},
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{X86::VBROADCASTSDYrm, 1, 64, rebuildSplatCst},
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{X86::VBROADCASTF128rm, 1, 128, rebuildSplatCst}},
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256, 1);
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case X86::VMOVAPDZ128rm:
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case X86::VMOVAPSZ128rm:
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case X86::VMOVUPDZ128rm:
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case X86::VMOVUPSZ128rm:
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return FixupConstant({{X86::VMOVSSZrm, 1, 32, rebuildZeroUpperCst},
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{X86::VBROADCASTSSZ128rm, 1, 32, rebuildSplatCst},
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{X86::VMOVSDZrm, 1, 64, rebuildZeroUpperCst},
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{X86::VMOVDDUPZ128rm, 1, 64, rebuildSplatCst}},
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128, 1);
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case X86::VMOVAPDZ256rm:
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case X86::VMOVAPSZ256rm:
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case X86::VMOVUPDZ256rm:
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case X86::VMOVUPSZ256rm:
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return FixupConstant(
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{{X86::VBROADCASTSSZ256rm, 1, 32, rebuildSplatCst},
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{X86::VBROADCASTSDZ256rm, 1, 64, rebuildSplatCst},
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{X86::VBROADCASTF32X4Z256rm, 1, 128, rebuildSplatCst}},
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256, 1);
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case X86::VMOVAPDZrm:
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case X86::VMOVAPSZrm:
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case X86::VMOVUPDZrm:
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case X86::VMOVUPSZrm:
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return FixupConstant({{X86::VBROADCASTSSZrm, 1, 32, rebuildSplatCst},
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{X86::VBROADCASTSDZrm, 1, 64, rebuildSplatCst},
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{X86::VBROADCASTF32X4rm, 1, 128, rebuildSplatCst},
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{X86::VBROADCASTF64X4rm, 1, 256, rebuildSplatCst}},
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512, 1);
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/* Integer Loads */
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case X86::MOVDQArm:
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case X86::MOVDQUrm: {
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FixupEntry Fixups[] = {
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{HasSSE41 ? X86::PMOVSXBQrm : 0, 2, 8, rebuildSExtCst},
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{HasSSE41 ? X86::PMOVZXBQrm : 0, 2, 8, rebuildZExtCst},
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{X86::MOVDI2PDIrm, 1, 32, rebuildZeroUpperCst},
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{HasSSE41 ? X86::PMOVSXBDrm : 0, 4, 8, rebuildSExtCst},
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{HasSSE41 ? X86::PMOVZXBDrm : 0, 4, 8, rebuildZExtCst},
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{HasSSE41 ? X86::PMOVSXWQrm : 0, 2, 16, rebuildSExtCst},
|
|
{HasSSE41 ? X86::PMOVZXWQrm : 0, 2, 16, rebuildZExtCst},
|
|
{X86::MOVQI2PQIrm, 1, 64, rebuildZeroUpperCst},
|
|
{HasSSE41 ? X86::PMOVSXBWrm : 0, 8, 8, rebuildSExtCst},
|
|
{HasSSE41 ? X86::PMOVZXBWrm : 0, 8, 8, rebuildZExtCst},
|
|
{HasSSE41 ? X86::PMOVSXWDrm : 0, 4, 16, rebuildSExtCst},
|
|
{HasSSE41 ? X86::PMOVZXWDrm : 0, 4, 16, rebuildZExtCst},
|
|
{HasSSE41 ? X86::PMOVSXDQrm : 0, 2, 32, rebuildSExtCst},
|
|
{HasSSE41 ? X86::PMOVZXDQrm : 0, 2, 32, rebuildZExtCst}};
|
|
return FixupConstant(Fixups, 128, 1);
|
|
}
|
|
case X86::VMOVDQArm:
|
|
case X86::VMOVDQUrm: {
|
|
FixupEntry Fixups[] = {
|
|
{HasAVX2 ? X86::VPBROADCASTBrm : 0, 1, 8, rebuildSplatCst},
|
|
{HasAVX2 ? X86::VPBROADCASTWrm : 0, 1, 16, rebuildSplatCst},
|
|
{X86::VPMOVSXBQrm, 2, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBQrm, 2, 8, rebuildZExtCst},
|
|
{X86::VMOVDI2PDIrm, 1, 32, rebuildZeroUpperCst},
|
|
{HasAVX2 ? X86::VPBROADCASTDrm : X86::VBROADCASTSSrm, 1, 32,
|
|
rebuildSplatCst},
|
|
{X86::VPMOVSXBDrm, 4, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBDrm, 4, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWQrm, 2, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWQrm, 2, 16, rebuildZExtCst},
|
|
{X86::VMOVQI2PQIrm, 1, 64, rebuildZeroUpperCst},
|
|
{HasAVX2 ? X86::VPBROADCASTQrm : X86::VMOVDDUPrm, 1, 64,
|
|
rebuildSplatCst},
|
|
{X86::VPMOVSXBWrm, 8, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBWrm, 8, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWDrm, 4, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWDrm, 4, 16, rebuildZExtCst},
|
|
{X86::VPMOVSXDQrm, 2, 32, rebuildSExtCst},
|
|
{X86::VPMOVZXDQrm, 2, 32, rebuildZExtCst}};
|
|
return FixupConstant(Fixups, 128, 1);
|
|
}
|
|
case X86::VMOVDQAYrm:
|
|
case X86::VMOVDQUYrm: {
|
|
FixupEntry Fixups[] = {
|
|
{HasAVX2 ? X86::VPBROADCASTBYrm : 0, 1, 8, rebuildSplatCst},
|
|
{HasAVX2 ? X86::VPBROADCASTWYrm : 0, 1, 16, rebuildSplatCst},
|
|
{HasAVX2 ? X86::VPBROADCASTDYrm : X86::VBROADCASTSSYrm, 1, 32,
|
|
rebuildSplatCst},
|
|
{HasAVX2 ? X86::VPMOVSXBQYrm : 0, 4, 8, rebuildSExtCst},
|
|
{HasAVX2 ? X86::VPMOVZXBQYrm : 0, 4, 8, rebuildZExtCst},
|
|
{HasAVX2 ? X86::VPBROADCASTQYrm : X86::VBROADCASTSDYrm, 1, 64,
|
|
rebuildSplatCst},
|
|
{HasAVX2 ? X86::VPMOVSXBDYrm : 0, 8, 8, rebuildSExtCst},
|
|
{HasAVX2 ? X86::VPMOVZXBDYrm : 0, 8, 8, rebuildZExtCst},
|
|
{HasAVX2 ? X86::VPMOVSXWQYrm : 0, 4, 16, rebuildSExtCst},
|
|
{HasAVX2 ? X86::VPMOVZXWQYrm : 0, 4, 16, rebuildZExtCst},
|
|
{HasAVX2 ? X86::VBROADCASTI128rm : X86::VBROADCASTF128rm, 1, 128,
|
|
rebuildSplatCst},
|
|
{HasAVX2 ? X86::VPMOVSXBWYrm : 0, 16, 8, rebuildSExtCst},
|
|
{HasAVX2 ? X86::VPMOVZXBWYrm : 0, 16, 8, rebuildZExtCst},
|
|
{HasAVX2 ? X86::VPMOVSXWDYrm : 0, 8, 16, rebuildSExtCst},
|
|
{HasAVX2 ? X86::VPMOVZXWDYrm : 0, 8, 16, rebuildZExtCst},
|
|
{HasAVX2 ? X86::VPMOVSXDQYrm : 0, 4, 32, rebuildSExtCst},
|
|
{HasAVX2 ? X86::VPMOVZXDQYrm : 0, 4, 32, rebuildZExtCst}};
|
|
return FixupConstant(Fixups, 256, 1);
|
|
}
|
|
case X86::VMOVDQA32Z128rm:
|
|
case X86::VMOVDQA64Z128rm:
|
|
case X86::VMOVDQU32Z128rm:
|
|
case X86::VMOVDQU64Z128rm: {
|
|
FixupEntry Fixups[] = {
|
|
{HasBWI ? X86::VPBROADCASTBZ128rm : 0, 1, 8, rebuildSplatCst},
|
|
{HasBWI ? X86::VPBROADCASTWZ128rm : 0, 1, 16, rebuildSplatCst},
|
|
{X86::VPMOVSXBQZ128rm, 2, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBQZ128rm, 2, 8, rebuildZExtCst},
|
|
{X86::VMOVDI2PDIZrm, 1, 32, rebuildZeroUpperCst},
|
|
{X86::VPBROADCASTDZ128rm, 1, 32, rebuildSplatCst},
|
|
{X86::VPMOVSXBDZ128rm, 4, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBDZ128rm, 4, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWQZ128rm, 2, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWQZ128rm, 2, 16, rebuildZExtCst},
|
|
{X86::VMOVQI2PQIZrm, 1, 64, rebuildZeroUpperCst},
|
|
{X86::VPBROADCASTQZ128rm, 1, 64, rebuildSplatCst},
|
|
{HasBWI ? X86::VPMOVSXBWZ128rm : 0, 8, 8, rebuildSExtCst},
|
|
{HasBWI ? X86::VPMOVZXBWZ128rm : 0, 8, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWDZ128rm, 4, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWDZ128rm, 4, 16, rebuildZExtCst},
|
|
{X86::VPMOVSXDQZ128rm, 2, 32, rebuildSExtCst},
|
|
{X86::VPMOVZXDQZ128rm, 2, 32, rebuildZExtCst}};
|
|
return FixupConstant(Fixups, 128, 1);
|
|
}
|
|
case X86::VMOVDQA32Z256rm:
|
|
case X86::VMOVDQA64Z256rm:
|
|
case X86::VMOVDQU32Z256rm:
|
|
case X86::VMOVDQU64Z256rm: {
|
|
FixupEntry Fixups[] = {
|
|
{HasBWI ? X86::VPBROADCASTBZ256rm : 0, 1, 8, rebuildSplatCst},
|
|
{HasBWI ? X86::VPBROADCASTWZ256rm : 0, 1, 16, rebuildSplatCst},
|
|
{X86::VPBROADCASTDZ256rm, 1, 32, rebuildSplatCst},
|
|
{X86::VPMOVSXBQZ256rm, 4, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBQZ256rm, 4, 8, rebuildZExtCst},
|
|
{X86::VPBROADCASTQZ256rm, 1, 64, rebuildSplatCst},
|
|
{X86::VPMOVSXBDZ256rm, 8, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBDZ256rm, 8, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWQZ256rm, 4, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWQZ256rm, 4, 16, rebuildZExtCst},
|
|
{X86::VBROADCASTI32X4Z256rm, 1, 128, rebuildSplatCst},
|
|
{HasBWI ? X86::VPMOVSXBWZ256rm : 0, 16, 8, rebuildSExtCst},
|
|
{HasBWI ? X86::VPMOVZXBWZ256rm : 0, 16, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWDZ256rm, 8, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWDZ256rm, 8, 16, rebuildZExtCst},
|
|
{X86::VPMOVSXDQZ256rm, 4, 32, rebuildSExtCst},
|
|
{X86::VPMOVZXDQZ256rm, 4, 32, rebuildZExtCst}};
|
|
return FixupConstant(Fixups, 256, 1);
|
|
}
|
|
case X86::VMOVDQA32Zrm:
|
|
case X86::VMOVDQA64Zrm:
|
|
case X86::VMOVDQU32Zrm:
|
|
case X86::VMOVDQU64Zrm: {
|
|
FixupEntry Fixups[] = {
|
|
{HasBWI ? X86::VPBROADCASTBZrm : 0, 1, 8, rebuildSplatCst},
|
|
{HasBWI ? X86::VPBROADCASTWZrm : 0, 1, 16, rebuildSplatCst},
|
|
{X86::VPBROADCASTDZrm, 1, 32, rebuildSplatCst},
|
|
{X86::VPBROADCASTQZrm, 1, 64, rebuildSplatCst},
|
|
{X86::VPMOVSXBQZrm, 8, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBQZrm, 8, 8, rebuildZExtCst},
|
|
{X86::VBROADCASTI32X4rm, 1, 128, rebuildSplatCst},
|
|
{X86::VPMOVSXBDZrm, 16, 8, rebuildSExtCst},
|
|
{X86::VPMOVZXBDZrm, 16, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWQZrm, 8, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWQZrm, 8, 16, rebuildZExtCst},
|
|
{X86::VBROADCASTI64X4rm, 1, 256, rebuildSplatCst},
|
|
{HasBWI ? X86::VPMOVSXBWZrm : 0, 32, 8, rebuildSExtCst},
|
|
{HasBWI ? X86::VPMOVZXBWZrm : 0, 32, 8, rebuildZExtCst},
|
|
{X86::VPMOVSXWDZrm, 16, 16, rebuildSExtCst},
|
|
{X86::VPMOVZXWDZrm, 16, 16, rebuildZExtCst},
|
|
{X86::VPMOVSXDQZrm, 8, 32, rebuildSExtCst},
|
|
{X86::VPMOVZXDQZrm, 8, 32, rebuildZExtCst}};
|
|
return FixupConstant(Fixups, 512, 1);
|
|
}
|
|
}
|
|
|
|
auto ConvertToBroadcastAVX512 = [&](unsigned OpSrc32, unsigned OpSrc64) {
|
|
unsigned OpBcst32 = 0, OpBcst64 = 0;
|
|
unsigned OpNoBcst32 = 0, OpNoBcst64 = 0;
|
|
if (OpSrc32) {
|
|
if (const X86FoldTableEntry *Mem2Bcst =
|
|
llvm::lookupBroadcastFoldTableBySize(OpSrc32, 32)) {
|
|
OpBcst32 = Mem2Bcst->DstOp;
|
|
OpNoBcst32 = Mem2Bcst->Flags & TB_INDEX_MASK;
|
|
}
|
|
}
|
|
if (OpSrc64) {
|
|
if (const X86FoldTableEntry *Mem2Bcst =
|
|
llvm::lookupBroadcastFoldTableBySize(OpSrc64, 64)) {
|
|
OpBcst64 = Mem2Bcst->DstOp;
|
|
OpNoBcst64 = Mem2Bcst->Flags & TB_INDEX_MASK;
|
|
}
|
|
}
|
|
assert(((OpBcst32 == 0) || (OpBcst64 == 0) || (OpNoBcst32 == OpNoBcst64)) &&
|
|
"OperandNo mismatch");
|
|
|
|
if (OpBcst32 || OpBcst64) {
|
|
unsigned OpNo = OpBcst32 == 0 ? OpNoBcst64 : OpNoBcst32;
|
|
FixupEntry Fixups[] = {{(int)OpBcst32, 32, 32, rebuildSplatCst},
|
|
{(int)OpBcst64, 64, 64, rebuildSplatCst}};
|
|
// TODO: Add support for RegBitWidth, but currently rebuildSplatCst
|
|
// doesn't require it (defaults to Constant::getPrimitiveSizeInBits).
|
|
return FixupConstant(Fixups, 0, OpNo);
|
|
}
|
|
return false;
|
|
};
|
|
|
|
// Attempt to find a AVX512 mapping from a full width memory-fold instruction
|
|
// to a broadcast-fold instruction variant.
|
|
if ((MI.getDesc().TSFlags & X86II::EncodingMask) == X86II::EVEX)
|
|
return ConvertToBroadcastAVX512(Opc, Opc);
|
|
|
|
// Reverse the X86InstrInfo::setExecutionDomainCustom EVEX->VEX logic
|
|
// conversion to see if we can convert to a broadcasted (integer) logic op.
|
|
if (HasVLX && !HasDQI) {
|
|
unsigned OpSrc32 = 0, OpSrc64 = 0;
|
|
switch (Opc) {
|
|
case X86::VANDPDrm:
|
|
case X86::VANDPSrm:
|
|
case X86::VPANDrm:
|
|
OpSrc32 = X86 ::VPANDDZ128rm;
|
|
OpSrc64 = X86 ::VPANDQZ128rm;
|
|
break;
|
|
case X86::VANDPDYrm:
|
|
case X86::VANDPSYrm:
|
|
case X86::VPANDYrm:
|
|
OpSrc32 = X86 ::VPANDDZ256rm;
|
|
OpSrc64 = X86 ::VPANDQZ256rm;
|
|
break;
|
|
case X86::VANDNPDrm:
|
|
case X86::VANDNPSrm:
|
|
case X86::VPANDNrm:
|
|
OpSrc32 = X86 ::VPANDNDZ128rm;
|
|
OpSrc64 = X86 ::VPANDNQZ128rm;
|
|
break;
|
|
case X86::VANDNPDYrm:
|
|
case X86::VANDNPSYrm:
|
|
case X86::VPANDNYrm:
|
|
OpSrc32 = X86 ::VPANDNDZ256rm;
|
|
OpSrc64 = X86 ::VPANDNQZ256rm;
|
|
break;
|
|
case X86::VORPDrm:
|
|
case X86::VORPSrm:
|
|
case X86::VPORrm:
|
|
OpSrc32 = X86 ::VPORDZ128rm;
|
|
OpSrc64 = X86 ::VPORQZ128rm;
|
|
break;
|
|
case X86::VORPDYrm:
|
|
case X86::VORPSYrm:
|
|
case X86::VPORYrm:
|
|
OpSrc32 = X86 ::VPORDZ256rm;
|
|
OpSrc64 = X86 ::VPORQZ256rm;
|
|
break;
|
|
case X86::VXORPDrm:
|
|
case X86::VXORPSrm:
|
|
case X86::VPXORrm:
|
|
OpSrc32 = X86 ::VPXORDZ128rm;
|
|
OpSrc64 = X86 ::VPXORQZ128rm;
|
|
break;
|
|
case X86::VXORPDYrm:
|
|
case X86::VXORPSYrm:
|
|
case X86::VPXORYrm:
|
|
OpSrc32 = X86 ::VPXORDZ256rm;
|
|
OpSrc64 = X86 ::VPXORQZ256rm;
|
|
break;
|
|
}
|
|
if (OpSrc32 || OpSrc64)
|
|
return ConvertToBroadcastAVX512(OpSrc32, OpSrc64);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool X86FixupVectorConstantsPass::runOnMachineFunction(MachineFunction &MF) {
|
|
LLVM_DEBUG(dbgs() << "Start X86FixupVectorConstants\n";);
|
|
bool Changed = false;
|
|
ST = &MF.getSubtarget<X86Subtarget>();
|
|
TII = ST->getInstrInfo();
|
|
SM = &ST->getSchedModel();
|
|
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
if (processInstruction(MF, MBB, MI)) {
|
|
++NumInstChanges;
|
|
Changed = true;
|
|
}
|
|
}
|
|
}
|
|
LLVM_DEBUG(dbgs() << "End X86FixupVectorConstants\n";);
|
|
return Changed;
|
|
}
|