6a17929e9f
This is mostly NFC but some output does change due to consistently inserting into poison rather than undef and using i64 as the index type for inserts.
401 lines
9.7 KiB
LLVM
401 lines
9.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
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define i47 @shl_by_0(i47 %A) {
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; CHECK-LABEL: @shl_by_0(
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; CHECK-NEXT: ret i47 [[A:%.*]]
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;
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%B = shl i47 %A, 0
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ret i47 %B
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}
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define i41 @shl_0(i41 %X) {
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; CHECK-LABEL: @shl_0(
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; CHECK-NEXT: ret i41 0
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;
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%B = shl i41 0, %X
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ret i41 %B
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}
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define <2 x i41> @shl_0_vec_undef_elt(<2 x i41> %X) {
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; CHECK-LABEL: @shl_0_vec_undef_elt(
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; CHECK-NEXT: ret <2 x i41> zeroinitializer
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;
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%B = shl <2 x i41> <i41 0, i41 undef>, %X
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ret <2 x i41> %B
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}
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define i41 @ashr_by_0(i41 %A) {
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; CHECK-LABEL: @ashr_by_0(
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; CHECK-NEXT: ret i41 [[A:%.*]]
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;
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%B = ashr i41 %A, 0
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ret i41 %B
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}
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define i39 @ashr_0(i39 %X) {
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; CHECK-LABEL: @ashr_0(
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; CHECK-NEXT: ret i39 0
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;
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%B = ashr i39 0, %X
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ret i39 %B
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}
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define <2 x i141> @ashr_0_vec_undef_elt(<2 x i141> %X) {
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; CHECK-LABEL: @ashr_0_vec_undef_elt(
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; CHECK-NEXT: ret <2 x i141> zeroinitializer
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;
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%B = shl <2 x i141> <i141 undef, i141 0>, %X
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ret <2 x i141> %B
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}
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define i55 @lshr_by_bitwidth(i55 %A) {
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; CHECK-LABEL: @lshr_by_bitwidth(
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; CHECK-NEXT: ret i55 poison
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;
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%B = lshr i55 %A, 55
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ret i55 %B
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}
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define i32 @shl_by_bitwidth(i32 %A) {
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; CHECK-LABEL: @shl_by_bitwidth(
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; CHECK-NEXT: ret i32 poison
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;
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%B = shl i32 %A, 32
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ret i32 %B
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}
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define <4 x i32> @lshr_by_bitwidth_splat(<4 x i32> %A) {
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; CHECK-LABEL: @lshr_by_bitwidth_splat(
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; CHECK-NEXT: ret <4 x i32> poison
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;
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%B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out
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ret <4 x i32> %B
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}
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define <4 x i32> @lshr_by_0_splat(<4 x i32> %A) {
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; CHECK-LABEL: @lshr_by_0_splat(
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; CHECK-NEXT: ret <4 x i32> [[A:%.*]]
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;
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%B = lshr <4 x i32> %A, zeroinitializer
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ret <4 x i32> %B
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}
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define <4 x i32> @shl_by_bitwidth_splat(<4 x i32> %A) {
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; CHECK-LABEL: @shl_by_bitwidth_splat(
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; CHECK-NEXT: ret <4 x i32> poison
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;
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%B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out
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ret <4 x i32> %B
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}
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define i32 @ashr_undef() {
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; CHECK-LABEL: @ashr_undef(
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; CHECK-NEXT: ret i32 0
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;
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%B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef
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ret i32 %B
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}
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define i32 @ashr_undef_variable_shift_amount(i32 %A) {
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; CHECK-LABEL: @ashr_undef_variable_shift_amount(
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; CHECK-NEXT: ret i32 0
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;
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%B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef
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ret i32 %B
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}
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define i32 @ashr_all_ones(i32 %A) {
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; CHECK-LABEL: @ashr_all_ones(
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; CHECK-NEXT: ret i32 -1
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;
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%B = ashr i32 -1, %A
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ret i32 %B
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}
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define <3 x i8> @ashr_all_ones_vec_with_undef_elts(<3 x i8> %x, <3 x i8> %y) {
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; CHECK-LABEL: @ashr_all_ones_vec_with_undef_elts(
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; CHECK-NEXT: ret <3 x i8> <i8 -1, i8 -1, i8 -1>
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;
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%sh = ashr <3 x i8> <i8 undef, i8 -1, i8 undef>, %y
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ret <3 x i8> %sh
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}
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define i8 @lshr_by_sext_bool(i1 %x, i8 %y) {
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; CHECK-LABEL: @lshr_by_sext_bool(
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; CHECK-NEXT: ret i8 [[Y:%.*]]
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;
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%s = sext i1 %x to i8
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%r = lshr i8 %y, %s
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ret i8 %r
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}
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define <2 x i8> @lshr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
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; CHECK-LABEL: @lshr_by_sext_bool_vec(
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; CHECK-NEXT: ret <2 x i8> [[Y:%.*]]
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;
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%s = sext <2 x i1> %x to <2 x i8>
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%r = lshr <2 x i8> %y, %s
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ret <2 x i8> %r
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}
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define i8 @ashr_by_sext_bool(i1 %x, i8 %y) {
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; CHECK-LABEL: @ashr_by_sext_bool(
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; CHECK-NEXT: ret i8 [[Y:%.*]]
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;
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%s = sext i1 %x to i8
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%r = ashr i8 %y, %s
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ret i8 %r
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}
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define <2 x i8> @ashr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
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; CHECK-LABEL: @ashr_by_sext_bool_vec(
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; CHECK-NEXT: ret <2 x i8> [[Y:%.*]]
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;
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%s = sext <2 x i1> %x to <2 x i8>
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%r = ashr <2 x i8> %y, %s
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ret <2 x i8> %r
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}
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define i8 @shl_by_sext_bool(i1 %x, i8 %y) {
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; CHECK-LABEL: @shl_by_sext_bool(
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; CHECK-NEXT: ret i8 [[Y:%.*]]
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;
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%s = sext i1 %x to i8
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%r = shl i8 %y, %s
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ret i8 %r
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}
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define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
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; CHECK-LABEL: @shl_by_sext_bool_vec(
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; CHECK-NEXT: ret <2 x i8> [[Y:%.*]]
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;
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%s = sext <2 x i1> %x to <2 x i8>
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%r = shl <2 x i8> %y, %s
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ret <2 x i8> %r
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}
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define i64 @shl_or_shr(i32 %a, i32 %b) {
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; CHECK-LABEL: @shl_or_shr(
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; CHECK-NEXT: [[T1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: ret i64 [[T1]]
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;
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%t1 = zext i32 %a to i64
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%t2 = zext i32 %b to i64
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%t3 = shl nuw i64 %t1, 32
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%t4 = or i64 %t2, %t3
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%t5 = lshr i64 %t4, 32
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ret i64 %t5
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}
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; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated.
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define i64 @shl_or_shr2(i32 %a, i32 %b) {
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; CHECK-LABEL: @shl_or_shr2(
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; CHECK-NEXT: [[T1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[T2:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[T3:%.*]] = shl nuw i64 [[T1]], 31
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; CHECK-NEXT: [[T4:%.*]] = or i64 [[T2]], [[T3]]
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; CHECK-NEXT: [[T5:%.*]] = lshr i64 [[T4]], 31
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; CHECK-NEXT: ret i64 [[T5]]
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;
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%t1 = zext i32 %a to i64
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%t2 = zext i32 %b to i64
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%t3 = shl nuw i64 %t1, 31
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%t4 = or i64 %t2, %t3
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%t5 = lshr i64 %t4, 31
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ret i64 %t5
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}
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; Unit test for vector integer
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define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_or_shr1v(
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; CHECK-NEXT: [[T1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> [[T1]]
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;
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%t1 = zext <2 x i32> %a to <2 x i64>
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%t2 = zext <2 x i32> %b to <2 x i64>
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%t3 = shl nuw <2 x i64> %t1, <i64 32, i64 32>
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%t4 = or <2 x i64> %t3, %t2
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%t5 = lshr <2 x i64> %t4, <i64 32, i64 32>
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ret <2 x i64> %t5
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}
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; Negative unit test for vector integer
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define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_or_shr2v(
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; CHECK-NEXT: [[T1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
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; CHECK-NEXT: [[T2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64>
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; CHECK-NEXT: [[T3:%.*]] = shl nuw <2 x i64> [[T1]], <i64 31, i64 31>
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; CHECK-NEXT: [[T4:%.*]] = or <2 x i64> [[T2]], [[T3]]
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; CHECK-NEXT: [[T5:%.*]] = lshr <2 x i64> [[T4]], <i64 31, i64 31>
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; CHECK-NEXT: ret <2 x i64> [[T5]]
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;
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%t1 = zext <2 x i32> %a to <2 x i64>
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%t2 = zext <2 x i32> %b to <2 x i64>
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%t3 = shl nuw <2 x i64> %t1, <i64 31, i64 31>
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%t4 = or <2 x i64> %t2, %t3
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%t5 = lshr <2 x i64> %t4, <i64 31, i64 31>
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ret <2 x i64> %t5
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}
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define i32 @poison(i32 %x) {
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; CHECK-LABEL: @poison(
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; CHECK-NEXT: ret i32 poison
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;
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%v = lshr i32 %x, poison
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ret i32 %v
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}
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define i32 @poison2(i32 %x) {
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; CHECK-LABEL: @poison2(
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; CHECK-NEXT: ret i32 poison
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;
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%v = ashr i32 %x, poison
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ret i32 %v
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}
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define i32 @poison3(i32 %x) {
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; CHECK-LABEL: @poison3(
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; CHECK-NEXT: ret i32 poison
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;
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%v = shl i32 %x, poison
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ret i32 %v
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}
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define i32 @poison4(i32 %x) {
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; CHECK-LABEL: @poison4(
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; CHECK-NEXT: ret i32 poison
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;
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%v = lshr i32 poison, %x
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ret i32 %v
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}
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define i32 @poison5(i32 %x) {
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; CHECK-LABEL: @poison5(
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; CHECK-NEXT: ret i32 poison
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;
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%v = ashr i32 poison, %x
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ret i32 %v
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}
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define i32 @poison6(i32 %x) {
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; CHECK-LABEL: @poison6(
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; CHECK-NEXT: ret i32 poison
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;
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%v = shl i32 poison, %x
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ret i32 %v
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}
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define i32 @all_ones_left_right(i32 %x) {
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; CHECK-LABEL: @all_ones_left_right(
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; CHECK-NEXT: ret i32 -1
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;
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%left = shl i32 -1, %x
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%right = ashr i32 %left, %x
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ret i32 %right
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}
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define <2 x i7> @all_ones_left_right_splat(<2 x i7> %x) {
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; CHECK-LABEL: @all_ones_left_right_splat(
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; CHECK-NEXT: ret <2 x i7> <i7 -1, i7 -1>
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;
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%left = shl <2 x i7> <i7 -1, i7 -1>, %x
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%right = ashr <2 x i7> %left, %x
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ret <2 x i7> %right
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}
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; Poison could propagate, but undef must not.
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define <3 x i7> @all_ones_left_right_splat_poison_undef_elt(<3 x i7> %x) {
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; CHECK-LABEL: @all_ones_left_right_splat_poison_undef_elt(
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; CHECK-NEXT: ret <3 x i7> <i7 -1, i7 -1, i7 -1>
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;
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%left = shl <3 x i7> <i7 poison, i7 -1, i7 undef>, %x
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%right = ashr <3 x i7> %left, %x
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ret <3 x i7> %right
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}
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; negative test - must have -1
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define i32 @almost_all_ones_left_right(i32 %x) {
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; CHECK-LABEL: @almost_all_ones_left_right(
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; CHECK-NEXT: [[LEFT:%.*]] = shl i32 -2, [[X:%.*]]
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; CHECK-NEXT: [[RIGHT:%.*]] = ashr i32 [[LEFT]], [[X]]
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; CHECK-NEXT: ret i32 [[RIGHT]]
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;
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%left = shl i32 -2, %x
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%right = ashr i32 %left, %x
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ret i32 %right
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}
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; negative test - must have same shift amount
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define i32 @all_ones_left_right_not_same_shift(i32 %x, i32 %y) {
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; CHECK-LABEL: @all_ones_left_right_not_same_shift(
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; CHECK-NEXT: [[LEFT:%.*]] = shl i32 -1, [[X:%.*]]
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; CHECK-NEXT: [[RIGHT:%.*]] = ashr i32 [[LEFT]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[RIGHT]]
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;
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%left = shl i32 -1, %x
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%right = ashr i32 %left, %y
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ret i32 %right
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}
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; shift by splat of bitwidth or more is poison
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define <vscale x 4 x i16> @lshr_scalable_overshift(<vscale x 4 x i16> %va) {
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; CHECK-LABEL: @lshr_scalable_overshift(
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; CHECK-NEXT: ret <vscale x 4 x i16> poison
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;
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%vc = lshr <vscale x 4 x i16> %va, splat (i16 16)
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ret <vscale x 4 x i16> %vc
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}
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; shl nsw+nuw is 0
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define i8 @shl_nsw_nuw_7_eq_0(i8 %x) {
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; CHECK-LABEL: @shl_nsw_nuw_7_eq_0(
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; CHECK-NEXT: ret i8 0
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;
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%y = shl nsw nuw i8 %x, 7
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ret i8 %y
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}
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; Make sure we match the element width
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define <2 x i8> @shl_vec_nsw_nuw_7_eq_0(<2 x i8> %x) {
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; CHECK-LABEL: @shl_vec_nsw_nuw_7_eq_0(
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; CHECK-NEXT: ret <2 x i8> zeroinitializer
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;
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%y = shl nsw nuw <2 x i8> %x, <i8 7, i8 7>
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ret <2 x i8> %y
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}
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; negative test (missing nuw)
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define i8 @shl_nsw_7_fail_missing_nuw(i8 %x) {
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; CHECK-LABEL: @shl_nsw_7_fail_missing_nuw(
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; CHECK-NEXT: [[Y:%.*]] = shl nsw i8 [[X:%.*]], 7
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; CHECK-NEXT: ret i8 [[Y]]
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;
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%y = shl nsw i8 %x, 7
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ret i8 %y
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}
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; negative test (missing nsw)
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define i8 @shl_nuw_7_fail_missing_nsw(i8 %x) {
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; CHECK-LABEL: @shl_nuw_7_fail_missing_nsw(
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; CHECK-NEXT: [[Y:%.*]] = shl nuw i8 [[X:%.*]], 7
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; CHECK-NEXT: ret i8 [[Y]]
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;
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%y = shl nuw i8 %x, 7
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ret i8 %y
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}
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; negative test (shift value != bitwdth - 1)
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define i8 @shl_nsw_nuw_6_do_nothing(i8 %x) {
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; CHECK-LABEL: @shl_nsw_nuw_6_do_nothing(
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; CHECK-NEXT: [[Y:%.*]] = shl nuw nsw i8 [[X:%.*]], 6
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; CHECK-NEXT: ret i8 [[Y]]
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;
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%y = shl nsw nuw i8 %x, 6
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ret i8 %y
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}
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