9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
37 lines
1.5 KiB
LLVM
37 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
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@array = external addrspace(4) constant [32 x [800 x i32]], align 4
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; GCN-LABEL: {{^}}test_lsr_voidty:
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define amdgpu_kernel void @test_lsr_voidty() {
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entry:
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br label %for.body
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for.body: ; preds = %for.body.i, %entry
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br label %for.body.i
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for.body.i: ; preds = %for.body.i, %for.body
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%ij = phi i32 [ 0, %for.body ], [ %inc14, %for.body.i ]
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%tmp = load i32, ptr addrspace(5) undef, align 4
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%inc13 = or i32 %ij, 2
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%shl = shl i32 1, 0
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%and = and i32 %shl, %tmp
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%tobool = icmp eq i32 %and, 0
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%add = mul nuw nsw i32 %inc13, 5
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%tmp1 = zext i32 %add to i64
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%arrayidx8 = getelementptr inbounds [32 x [800 x i32]], ptr addrspace(4) @array, i64 0, i64 undef, i64 %tmp1
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%tmp2 = load i32, ptr addrspace(4) %arrayidx8, align 4
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%and9 = select i1 %tobool, i32 0, i32 %tmp2
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%xor = xor i32 undef, %and9
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%inc1 = or i32 %ij, 3
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%add2 = mul nuw nsw i32 %inc1, 5
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%add6 = add nuw nsw i32 %add2, 1
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%tmp3 = zext i32 %add6 to i64
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%arrayidx9 = getelementptr inbounds [32 x [800 x i32]], ptr addrspace(4) @array, i64 0, i64 undef, i64 %tmp3
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%tmp5 = load <4 x i32>, ptr addrspace(4) %arrayidx9, align 4
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%reorder_shuffle2 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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%tmp6 = select <4 x i1> undef, <4 x i32> zeroinitializer, <4 x i32> %reorder_shuffle2
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%inc14 = add nuw nsw i32 %ij, 4
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br i1 undef, label %for.body, label %for.body.i
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}
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