2fab927546
Check lines for some of these tests were regenerated. The difference is that with opaque pointers SCEVExpander always emits i8 GEPs, making the address calculation explicit. This is a known problem that will be solved long term by making all address calculations explicit.
88 lines
4.2 KiB
LLVM
88 lines
4.2 KiB
LLVM
; RUN: opt -passes=loop-vectorize < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-NO4
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; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=1 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO2,CHECK-NO4
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; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=2 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-NO4
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; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=4 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-4
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-none-none-eabi"
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; CHECK-LABEL: vld2
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; CHECK-2: vector.body
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; CHECK-NO2-NOT: vector.body
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define void @vld2(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
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entry:
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%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
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%0 = bitcast i16 %tmp.0.extract.trunc to half
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%mul = mul i32 %numCols, %numRows
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%shr = lshr i32 %mul, 2
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%cmp26 = icmp eq i32 %shr, 0
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br i1 %cmp26, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%pIn.addr.029 = phi ptr [ %add.ptr, %while.body ], [ %pIn, %entry ]
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%pOut.addr.028 = phi ptr [ %add.ptr7, %while.body ], [ %pOut, %entry ]
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%blkCnt.027 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]
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%1 = load half, ptr %pIn.addr.029, align 2
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%arrayidx2 = getelementptr inbounds half, ptr %pIn.addr.029, i32 1
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%2 = load half, ptr %arrayidx2, align 2
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%mul3 = fmul half %1, %0
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%mul4 = fmul half %2, %0
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store half %mul3, ptr %pOut.addr.028, align 2
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%arrayidx6 = getelementptr inbounds half, ptr %pOut.addr.028, i32 1
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store half %mul4, ptr %arrayidx6, align 2
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%add.ptr = getelementptr inbounds half, ptr %pIn.addr.029, i32 2
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%add.ptr7 = getelementptr inbounds half, ptr %pOut.addr.028, i32 2
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%dec = add nsw i32 %blkCnt.027, -1
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%cmp = icmp eq i32 %dec, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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; CHECK-LABEL: vld4
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; CHECK-4: vector.body
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; CHECK-NO4-NOT: vector.body
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define void @vld4(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
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entry:
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%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
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%0 = bitcast i16 %tmp.0.extract.trunc to half
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%mul = mul i32 %numCols, %numRows
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%shr = lshr i32 %mul, 2
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%cmp38 = icmp eq i32 %shr, 0
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br i1 %cmp38, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%pIn.addr.041 = phi ptr [ %add.ptr, %while.body ], [ %pIn, %entry ]
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%pOut.addr.040 = phi ptr [ %add.ptr13, %while.body ], [ %pOut, %entry ]
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%blkCnt.039 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]
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%1 = load half, ptr %pIn.addr.041, align 2
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%arrayidx2 = getelementptr inbounds half, ptr %pIn.addr.041, i32 1
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%2 = load half, ptr %arrayidx2, align 2
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%arrayidx3 = getelementptr inbounds half, ptr %pIn.addr.041, i32 2
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%3 = load half, ptr %arrayidx3, align 2
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%arrayidx4 = getelementptr inbounds half, ptr %pIn.addr.041, i32 3
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%4 = load half, ptr %arrayidx4, align 2
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%mul5 = fmul half %1, %0
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%mul6 = fmul half %2, %0
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%mul7 = fmul half %3, %0
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%mul8 = fmul half %4, %0
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store half %mul5, ptr %pOut.addr.040, align 2
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%arrayidx10 = getelementptr inbounds half, ptr %pOut.addr.040, i32 1
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store half %mul6, ptr %arrayidx10, align 2
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%arrayidx11 = getelementptr inbounds half, ptr %pOut.addr.040, i32 2
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store half %mul7, ptr %arrayidx11, align 2
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%arrayidx12 = getelementptr inbounds half, ptr %pOut.addr.040, i32 3
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store half %mul8, ptr %arrayidx12, align 2
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%add.ptr = getelementptr inbounds half, ptr %pIn.addr.041, i32 4
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%add.ptr13 = getelementptr inbounds half, ptr %pOut.addr.040, i32 4
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%dec = add nsw i32 %blkCnt.039, -1
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%cmp = icmp eq i32 %dec, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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attributes #0 = { "target-features"="+armv8.1-m.main,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-crypto,-d32,-fp-armv8,-fp-armv8sp,-neon,-vfp3,-vfp3sp,-vfp4,-vfp4sp" }
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