15d9d0fa8f
Some optimizations are apply after UF and VF have been chosen. This patch adds an extra print of the final VPlan just before codegen/execution. In the future, there will be additional transforms that are applied later (interleaving for example). PR: https://github.com/llvm/llvm-project/pull/82269
91 lines
3.4 KiB
LLVM
91 lines
3.4 KiB
LLVM
; RUN: opt -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=2 -disable-output -debug -S %s 2>&1 | FileCheck --check-prefixes=CHECK %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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; REQUIRES: asserts
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; Check if the vector loop condition can be simplified to true for a given
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; VF/IC combination.
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define void @test_tc_less_than_16(ptr %A, i64 %N) {
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; CHECK: LV: Scalarizing: %cmp =
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; CHECK-NEXT: VPlan 'Initial VPlan for VF={8},UF>=1' {
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; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
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; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count
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; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ph:
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; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i4 (trunc i64 %N to i4) to i64)
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
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; CHECK-NEXT: EMIT ir<%p.src> = WIDEN-POINTER-INDUCTION ir<%A>, 1
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; CHECK-NEXT: vp<[[VPTR:%.]]> = vector-pointer ir<%p.src>
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; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VPTR]]>
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; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%l>, ir<10>
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; CHECK-NEXT: vp<[[VPTR2:%.+]]> = vector-pointer ir<%p.src>
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; CHECK-NEXT: WIDEN store vp<[[VPTR2]]>, ir<%add>
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV:%.+]]>, vp<[[VFxUF]]>
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; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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;
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; CHECK: Executing best plan with VF=8, UF=2
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; CHECK-NEXT: VPlan 'Final VPlan for VF={8},UF={2}' {
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; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
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; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ph:
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; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i4 (trunc i64 %N to i4) to i64)
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
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; CHECK-NEXT: EMIT ir<%p.src> = WIDEN-POINTER-INDUCTION ir<%A>, 1
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; CHECK-NEXT: vp<[[VPTR:%.]]> = vector-pointer ir<%p.src>
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; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VPTR]]>
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; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%l>, ir<10>
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; CHECK-NEXT: vp<[[VPTR2:%.+]]> = vector-pointer ir<%p.src>
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; CHECK-NEXT: WIDEN store vp<[[VPTR2]]>, ir<%add>
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV:%.+]]>, vp<[[VFxUF]]>
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; CHECK-NEXT: EMIT branch-on-cond ir<true>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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;
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entry:
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%and = and i64 %N, 15
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br label %loop
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loop:
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%iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ]
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%p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ]
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%p.src.next = getelementptr inbounds i8, ptr %p.src, i64 1
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%l = load i8, ptr %p.src, align 1
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%add = add nsw i8 %l, 10
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store i8 %add, ptr %p.src
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%iv.next = add nsw i64 %iv, -1
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%cmp = icmp eq i64 %iv.next, 0
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br i1 %cmp, label %exit, label %loop
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exit:
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ret void
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}
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