d9962c400f
This flag indicates that every bit is known to be zero in at least one of the inputs. This allows the Or to be treated as an Add since there is no possibility of a carry from any bit. If the flag is present and this property does not hold, the result is poison. This makes it easier to reverse the InstCombine transform that turns Add into Or. This is inspired by a comment here https://github.com/llvm/llvm-project/pull/71955#discussion_r1391614578 Discourse thread https://discourse.llvm.org/t/rfc-add-or-disjoint-flag/75036
157 lines
3.7 KiB
LLVM
157 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=simplifycfg -hoist-common-insts=true -S | FileCheck %s
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; RUN: opt < %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true -S | FileCheck %s
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define void @foo(i1 %C, ptr %P) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: store i32 7, ptr [[P:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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br i1 %C, label %T, label %F
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T: ; preds = %0
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store i32 7, ptr %P
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ret void
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F: ; preds = %0
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store i32 7, ptr %P
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ret void
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}
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define void @foo_switch(i64 %C, ptr %P) {
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; CHECK-LABEL: @foo_switch(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: store i32 7, ptr [[P:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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switch i64 %C, label %bb0 [
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i64 1, label %bb1
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i64 2, label %bb2
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]
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bb0: ; preds = %0
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store i32 7, ptr %P
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ret void
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bb1: ; preds = %0
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store i32 7, ptr %P
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ret void
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bb2: ; preds = %0
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store i32 7, ptr %P
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ret void
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}
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define float @PR39535min(float %x) {
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; CHECK-LABEL: @PR39535min(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TOBOOL:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
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; CHECK-NEXT: [[DOTX:%.*]] = select fast i1 [[TOBOOL]], float 0.000000e+00, float [[X]]
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; CHECK-NEXT: ret float [[DOTX]]
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;
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entry:
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%tobool = fcmp une float %x, 0.0
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br i1 %tobool, label %cond.true, label %cond.false
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cond.true:
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br label %cond.end
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cond.false:
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br label %cond.end
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cond.end:
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%cond = phi fast float [ 0.0, %cond.true ], [ %x, %cond.false ]
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ret float %cond
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}
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define float @PR39535min_switch(i64 %i, float %x) {
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; CHECK-LABEL: @PR39535min_switch(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i64 [[I:%.*]], label [[END:%.*]] [
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; CHECK-NEXT: i64 1, label [[BB1:%.*]]
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; CHECK-NEXT: i64 2, label [[BB2:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: bb2:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[COND:%.*]] = phi fast float [ [[X:%.*]], [[BB1]] ], [ [[X]], [[BB2]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret float [[COND]]
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;
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entry:
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switch i64 %i, label %bb0 [
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i64 1, label %bb1
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i64 2, label %bb2
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]
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bb0:
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br label %end
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bb1:
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br label %end
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bb2:
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br label %end
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end:
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%cond = phi fast float [ 0.0, %bb0 ], [ %x, %bb1 ], [ %x, %bb2 ]
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ret float %cond
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}
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define i32 @hoist_zext_flags_preserve(i1 %C, i8 %x) {
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; CHECK-LABEL: @hoist_zext_flags_preserve(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: [[Z1:%.*]] = zext nneg i8 [[X:%.*]] to i32
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; CHECK-NEXT: ret i32 [[Z1]]
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;
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br i1 %C, label %T, label %F
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T:
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%z1 = zext nneg i8 %x to i32
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ret i32 %z1
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F:
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%z2 = zext nneg i8 %x to i32
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ret i32 %z2
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}
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define i32 @hoist_zext_flags_drop(i1 %C, i8 %x) {
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; CHECK-LABEL: @hoist_zext_flags_drop(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: ret i32 [[Z1]]
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;
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br i1 %C, label %T, label %F
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T:
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%z1 = zext nneg i8 %x to i32
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ret i32 %z1
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F:
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%z2 = zext i8 %x to i32
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ret i32 %z2
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}
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define i32 @hoist_or_flags_preserve(i1 %C, i32 %x, i32 %y) {
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; CHECK-LABEL: @hoist_or_flags_preserve(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: [[Z1:%.*]] = or disjoint i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[Z1]]
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;
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br i1 %C, label %T, label %F
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T:
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%z1 = or disjoint i32 %x, %y
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ret i32 %z1
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F:
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%z2 = or disjoint i32 %x, %y
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ret i32 %z2
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}
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define i32 @hoist_or_flags_drop(i1 %C, i32 %x, i32 %y) {
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; CHECK-LABEL: @hoist_or_flags_drop(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: [[Z1:%.*]] = or i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[Z1]]
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;
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br i1 %C, label %T, label %F
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T:
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%z1 = or i32 %x, %y
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ret i32 %z1
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F:
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%z2 = or disjoint i32 %x, %y
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ret i32 %z2
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}
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