1c466477ad
Currenlty assume x18 is used as pointer to shadow call stack. User shall pass flags: "-fsanitize=shadow-call-stack -ffixed-x18" Runtime supported is needed to setup x18. If SCS is desired, all parts of the program should be built with -ffixed-x18 to maintain inter-operatability. There's no particuluar reason that we must use x18 as SCS pointer. Any register may be used, as long as it does not have designated purpose already, like RA or passing call arguments. Differential Revision: https://reviews.llvm.org/D84414
85 lines
2.9 KiB
C++
85 lines
2.9 KiB
C++
#include "RISCVBaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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namespace RISCVSysReg {
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#define GET_SysRegsList_IMPL
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#include "RISCVGenSystemOperands.inc"
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} // namespace RISCVSysReg
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namespace RISCVABI {
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ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
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StringRef ABIName) {
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auto TargetABI = getTargetABI(ABIName);
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bool IsRV64 = TT.isArch64Bit();
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bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
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if (!ABIName.empty() && TargetABI == ABI_Unknown) {
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errs()
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<< "'" << ABIName
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<< "' is not a recognized ABI for this target (ignoring target-abi)\n";
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} else if (ABIName.startswith("ilp32") && IsRV64) {
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errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
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"target-abi)\n";
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TargetABI = ABI_Unknown;
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} else if (ABIName.startswith("lp64") && !IsRV64) {
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errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
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"target-abi)\n";
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TargetABI = ABI_Unknown;
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} else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
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// TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
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errs()
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<< "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
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TargetABI = ABI_Unknown;
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}
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if (TargetABI != ABI_Unknown)
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return TargetABI;
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// For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given
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// or an invalid/unrecognised string is given. In the future, it might be
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// worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when
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// hardware support for floating point is present.
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if (IsRV32E)
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return ABI_ILP32E;
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if (IsRV64)
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return ABI_LP64;
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return ABI_ILP32;
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}
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ABI getTargetABI(StringRef ABIName) {
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auto TargetABI = StringSwitch<ABI>(ABIName)
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.Case("ilp32", ABI_ILP32)
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.Case("ilp32f", ABI_ILP32F)
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.Case("ilp32d", ABI_ILP32D)
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.Case("ilp32e", ABI_ILP32E)
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.Case("lp64", ABI_LP64)
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.Case("lp64f", ABI_LP64F)
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.Case("lp64d", ABI_LP64D)
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.Default(ABI_Unknown);
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return TargetABI;
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}
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// To avoid the BP value clobbered by a function call, we need to choose a
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// callee saved register to save the value. RV32E only has X8 and X9 as callee
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// saved registers and X8 will be used as fp. So we choose X9 as bp.
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Register getBPReg() { return RISCV::X9; }
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// Returns the register holding shadow call stack pointer.
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Register getSCSPReg() { return RISCV::X18; }
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} // namespace RISCVABI
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namespace RISCVFeatures {
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void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
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if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
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report_fatal_error("RV32E can't be enabled for an RV64 target");
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}
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} // namespace RISCVFeatures
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} // namespace llvm
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